HYB18T512400AC Infineon Technologies AG, HYB18T512400AC Datasheet - Page 4

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HYB18T512400AC

Manufacturer Part Number
HYB18T512400AC
Description
DDR2 Registered Memory Modules
Manufacturer
Infineon Technologies AG
Datasheet
1.3 Components on Modules and RawCard
1.4 Pin Definition and Function
Data Sheet
Preliminary
1024 MB
1024 MB
2048 MB
2048 MB
A[13:0]
A11, A[9:0]
A10/AP
BA[1:0]
CK0
CK0
RAS
CAS
WE
CS[1:0]
CKE[1:0]
ODT[1:0]
DQ[63:0]
1) Active termination only applies to DQ, DQS, DQS and DM signals
2) When low, all register outputs will be driven low and the PLL clocks to the DRAM and registers will be set to low levels (the
3) CS1, ODT1 and CKE1 are used on dual rank modules only
4) Column address A11 is used on modules based on x4 organised 512Mb DDR2 components only.
Density
512 MB
For a detailed description of all functionalities of the DRAM components on these modules see the referenced component data
sheet
DIMM
PLL will remain synchronized with the input clock
Pin Name
reference datasheet
DRAM components
HYB18T512800AC
HYB18T512800AF
HYB18T512800AC
HYB18T512800AF
HYB18T512400AC
HYB18T512400AF
HYB18T512400AC
HYB18T512400AF
HYB18T512400AC
HYB18T512400AF
Row Address Inputs
Column Address Inputs
Column Address Input for Auto-
Precharge
SDRAM Bank Selects
Clock input
(positive line of differential pair)
Clock input
(negative line of differential pair)
Row Address Strobe
Column Address Strobe
Read/Write Input
Chip Selects
Clock Enable
Active termination control lines
Data Input/Output
Description
3)
3)
1:10, 1.8V, CU877
1:10, 1.8V, CU877
1:10, 1.8V, CU877
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
4)
PLL
tbd.
tbd.
1) 3)
4
CB[7:0]
DQS[8:0]
DM[8:0] /
DQS[17:9]
DQS[17:0]
SCL
SDA
SA[2:0]
V
V
V
V
RESET
NC
DD
REF
SS
DDSPD
Registered DDR2 SDRAM Modules
Pin Name
1:1 25-bit 1.8V SSTU32864
1:2 14-bit 1.8V SSTU32864
1:2 14-bit 1.8V SSTU32864
Register
DIMM ECC Check Bits
SDRAM low data strobes
SDRAM low data mask/
high data strobes
SDRAM differential data strobes
Serial bus clock
Serial bus data line
slave address select
Power (+ 1.8 V)
I/O reference supply
Ground
EEPROM power supply
Register and PLL control pin
No connection
tbd.
tbd.
Description
Rev. 0.85, 2004-04
Raw Card
tbd.
tbd.
A
B
C
2)

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