UPSD3233 STMicroelectronics, UPSD3233 Datasheet - Page 156

no-image

UPSD3233

Manufacturer Part Number
UPSD3233
Description
Flash Programmable System Devices with 8032 Microcontroller Core
Manufacturer
STMicroelectronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPSD3233
Manufacturer:
ST
0
Part Number:
UPSD3233A-40T6
Manufacturer:
ST
0
Part Number:
UPSD3233A-40U6
Manufacturer:
ST
0
Part Number:
UPSD3233B
Manufacturer:
ST
0
Part Number:
UPSD3233B-24T6
Manufacturer:
ST
0
Part Number:
UPSD3233B-40T6
Manufacturer:
ST
Quantity:
5 530
Part Number:
UPSD3233B-40T6
Manufacturer:
ST
Quantity:
586
Part Number:
UPSD3233B-40T6
Manufacturer:
ST
Quantity:
20 000
Part Number:
UPSD3233B-40U6
Manufacturer:
COSEL
Quantity:
100
Part Number:
UPSD3233B-40U6
Manufacturer:
ST
Quantity:
20 000
Part Number:
UPSD3233BV-24T6
Manufacturer:
ST
Quantity:
200
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Figure 78. Input to Output Disable / Enable
Table 121. CPLD Combinatorial Timing (5V Devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
Table 122. CPLD Combinatorial Timing (3V Devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
156/175
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
Symbol
PD
EA
ER
ARP
ARPW
ARD
PD
EA
ER
ARP
ARPW
ARD
(2)
(2)
2. t
2. t
output (80-pin package only)
output (80-pin package only)
PD
PD
for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
CPLD Input to CPLD Output
Enable
CPLD Input to CPLD Output
Disable
CPLD Register Clear or Preset
Delay
CPLD Register Clear or Preset
Pulse Width
CPLD Array Delay
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
CPLD Input to CPLD Output
Enable
CPLD Input to CPLD Output
Disable
CPLD Register Clear or
Preset Delay
CPLD Register Clear or
Preset Pulse Width
CPLD Array Delay
ENABLE/DISABLE
Parameter
Parameter
INPUT TO
OUTPUT
INPUT
Conditions
Conditions
macrocell
macrocell
Any
Any
tER
Min
Min
10
25
tEA
Max
Max
20
21
21
21
40
43
43
40
25
11
Aloc
Aloc
+ 2
+ 2
+ 4
+ 4
PT
PT
AI02863
Turbo
Turbo
+ 10
+ 10
+ 10
+ 10
+ 10
+ 20
+ 20
+ 20
+ 20
+ 20
Off
Off
rate
rate
Slew
Slew
– 2
– 2
– 2
– 2
– 6
– 6
– 6
– 6
(1)
(1)
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Related parts for UPSD3233