UPSD3233 STMicroelectronics, UPSD3233 Datasheet - Page 82

• Manufacturer Part Number: UPSD3233
• Description: Flash Programmable System Devices with 8032 Microcontroller Core
• Manufacturer: STMicroelectronics

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
DDC INTERFACE
The basic DDC unit consists of an I
and 256 bytes of SRAM for DDC data storage. The
8032 core is responsible of loading the contents of
the SRAM with the DDC data. The DDC unit has
the following features:
Figure 40. DDC Interface Block Diagram
82/175
Supports both DDC1 and DDC2b Modes.
Features 256 bytes of DDC data - initialized by
the 8032
SCL1
SDA1
VSYNC
EN
DDCCON
X
DAT
DDC2B+Interface
EX_
DDC2B/DDC2AB
Arbitration Logic
ENB
DDC1/DDC2
SW
Detection
X
DDC1
INT
DDC1
EN
2
SWH
S1ADR0
S1ADR1
INT
S1DAT
SISTA
C interface
SICON
DDCDAT
7
Initialization Synchronization
M0
Bus Clock Generator
DDC1 Hold Register
DDC1 Transmitter
Monitor Address
Monitor Address
Shift Register
INTR (from SISTA)
The interface signals for the DDC can be mapped
to pins in Port 4. The interface consists of the stan-
dard V
DDC signals. The conceptual block diagram is il-
lustrated in Figure 43.
Supports fully automatic operation of DDC1 and
DDC2b Modes
DDC operates in Slave Mode only.
SW Interrupt Mode available (existing design)
1
SYNC
0
INT
(P4.2), SDA (P4.0) and SCL (P4.1)
DDCADR
Address Pointer
RAMBUF
Buffer
RAM
AI06628