UPSD3233 STMicroelectronics, UPSD3233 Datasheet - Page 81

• Manufacturer Part Number: UPSD3233
• Description: Flash Programmable System Devices with 8032 Microcontroller Core
• Manufacturer: STMicroelectronics

Address Register (SxADR: S1ADR, S2ADR)
This 8-bit register may be loaded with the 7-bit
slave address to which the controller will respond
when programmed as a slave receive/transmitter.
The Start/Stop Hold Time Detection and System
Clock registers (Tables 57 and 58) are included in
Table 56. Address Register (SxADR)
Note: 1. SLA6 to SLA0: Own slave address.
Table 57. Start /Stop Hold Time Detection Register (S1SETUP, S2SETUP)
Table 58. System Cock of 40MHz
Table 59. System Clock Setup Examples
SFR
S2SETUP Register
SLA6
30MHz (f
20MHz (f
S1SETUP,
40MHz (f
8MHz (f
7
Value
Address
8Bh
FFh
00h
80h
81h
82h
...
...
System Clock
D1h
D2h
OSC
OSC
OSC
OSC
/2 -> 250ns)
/2 -> 66.6ns)
/2 -> 100ns)
/2 -> 50ns)
SLA5
Register Name Reset Value
6
S1SETUP
S2SETUP
Number of Sample
Clock (f
128EA
50ns)
12EA
1EA
1EA
2EA
3EA
...
...
OSC
SLA4
5
/2 ->
S2SETUP Register
S1SETUP,
00h
00h
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Value
8Bh
89h
86h
83h
Stop Hold Time
Required Start/
SLA3
4
6000ns
To control the start/stop hold time detection for the DDC module
in Slave Mode
To control the start/stop hold time detection for the multi-master
I²C module in Slave Mode
100ns
150ns
600ns
50ns
50ns
...
...
Number of Sample
the I
to work with the large range of MCU frequency val-
ues supported. For example, with a system clock
of 40MHz.
SLA2
3
2
C unit to specify the start/stop detection time
Clock
12 EA
9 EA
6 EA
3 EA
When Bit 7 (enable bit) = 0, the number of
sample clock is 1EA (ignore Bit 6 to Bit 0)
Fast Mode I²C Start/Stop hold time specification
SLA1
2
Note
Required Start/Stop Hold Time
Note
SLA0
1
600ns
600ns
600ns
750ns
—
0
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