AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 105

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

USER ACCESSIBLE REGISTERS
The PCnet-PCI II controller has three types of user
registers: the PCI configuration registers, the Control
and Status registers (CSR) and the Bus Control
registers (BCR).
The PCnet-PCI II controller implements all PCnet-ISA
(Am79C960) registers, all C-LANCE (Am79C90) regis-
ters, all ILACC (Am79C900) registers, plus a number of
additional registers. The PCnet-PCI II controller CSRs
are compatible with both the PCnet-ISA CSRs and all of
the C-LANCE CSRs upon power up. Compatibility to the
ILACC set of CSRs requires one access to the Software
Style register (BCR20, bits 7–0) to be performed. By
setting an appropriate value of the Software Style regis-
ter (BCR20, bits 7–0) the user can select a set of CSRs
that are compatible with the ILACC set of CSRs.
The PCI configuration registers can be accessed in any
data width. All other registers must be accessed accord-
ing to the I/O mode that is currently selected. When WIO
mode is selected, all other register locations are defined
to be 16 bits in width. When DWIO mode is selected, all
these register locations are defined to be 32 bits in
width, with the upper 16 bits of most register locations
marked as reserved locations with undefined values.
When performing register write operations in DWIO
mode, the upper 16 bits should always be written as
ZEROs. When performing register read operations in
DWIO mode, the upper 16 bits of I/O resources should
Table 21. I/O Map In DWord I/O Mode (DWIO = 1)
Offset
00h – 0Fh
10h
14h
18h
1Ch
AD[4:0]
0XX00
0XX00
10000
10100
11000
10000
10100
11000
No. of Bytes
BE[3:0]
0000
0000
0000
0000
0000
0000
0000
0000
16
4
4
4
4
Table 22. Legal I/O Accesses in Double Word I/O Mode (DWIO = 1)
Register
APROM
RDP
RAP (shared by RDP
and BDP)
Reset Register
BDP
Type
WR
WR
WR
WR
RD
RD
RD
RD
Comment
DWord Read of APROM Locations 3h (MSB) to 0h (LSB),
7h to 4h, Bh to 8h or Fh to Ch
DWord Read of RDP
DWord Read of RAP
DWord Read of Reset Register
DWord Write to APROM Locations 3h (MSB) to 0h (LSB), 7h to 4h, Bh to
8h or Fh to Ch
DWord Write to RDP
DWord Write to RAP
DWord Write to Reset Register
P R E L I M I N A R Y
Am79C970A
All I/O resources must be accessed in DWord quantities
and on DWord addresses. A read access other than
listed in the table below will yield undefined data, a write
operation may cause unexpected reprogramming of the
PCnet-PCI II controller control registers.
always be regarded as having undefined values, except
for CSR88.
PCnet-PCI II controller registers can be divided into
four groups:
PCI Configuration Registers
Registers that are intended to be initialized by the
system initialization procedure (e.g. BIOS device
initialization routine) to program the operation of the
PCnet-PCI II controller PCI bus interface.
Setup Registers
Registers that are intended to be initialized by the device
driver to program the operation of various PCnet-PCI II
controller features.
Running Registers
Registers that are intended to be used by the
device driver software once the PCnet-PCI II controller
is running to access status information and to pass
control information.
Test Registers
Registers that are intended to be used only for testing
and diagnostic purposes.
Below is a list of the registers that fall into each of the first
three categories. Those registers that are not included
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