AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 35

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

bit 7), which is hardwired to ONE. The PCnet-PCI II con-
troller is capable of detecting a memory cycle even
when its address phase immediately follows the data
phase of a transaction to a different target without any
Exclusive Access
The host can lock a set of transactions to the
PCnet-PCI II controller. The lock allows exclusive ac-
cess to the device and can be used to guarantee atomic
operations. The PCnet-PCI II controller transitions from
the unlocked to the locked state when LOCK is deas-
serted during the address phase of a transaction that se-
lects the device as the target. The controller stays in the
locked state until both FRAME and LOCK are
deasserted, or until the device signals a target abort.
Note that this protocol means the device locks itself on
any normal transaction. The controller will unlock
automatically at the end of a normal transaction, be-
cause FRAME and LOCK will be deasserted. The lock
spans over the whole slave address space. The lock
only applies to slave accesses. The PCnet-PCI II
controller might perform bus master cycles while being
locked in slave mode. When another master tries to
DEVSEL
FRAME
TRDY
STOP
IRDY
C/BE
PAR
CLK
AD
1
DEVSEL is sampled
ADDR
CMD
2
PAR
Figure 5. Expansion ROM Read
3
BE
P R E L I M I N A R Y
4
Am79C970A
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idle state in-between. There will be no contention on
the DEVSEL, TRDY and STOP signals, since the
PCnet-PCI II controller asserts DEVSEL on the second
clock after FRAME is asserted (medium timing).
access the PCnet-PCI II controller while it is in the
locked state, the device terminates the access with a
disconnect/retry sequence.
Slave Cycle Termination
There are three scenarios besides normal completion of
a transaction where the PCnet-PCI II controller is the
target of a slave cycle and it will terminate the access.
Disconnect When Busy
The PCnet-PCI II controller cannot service any slave ac-
cess while it is reading the contents of the Microwire
EEPROM. Simultaneous access is not possible to avoid
conflicts, since the Microwire EEPROM is used to initial-
ize some of the PCI configuration space locations and
most of the BCRs. The Microwire EEPROM read opera-
tion will always happen automatically after the deasser-
tion of the RST pin. In addition, the host can start the
42
43
DATA
44
PAR
45
19436A-8
AMD
35