AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 111

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

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0
PCI Expansion ROM Base Address Register
(Offset 30h)
The PCI Expansion ROM Base Address register is a
32-bit register that defines the base address, size and
address alignment of an Expansion ROM. It is located at
offset 30h in the PCI Configuration Space.
Bit
31–16ROMBASE
15–11ROMSIZE
MEMSPACE
TYPE
Name
address space is a Reset regis-
ter, the order of the read ac-
cesses is important.
Memory type indicator. Read as
ZEROs, write operations have
no effect. Indicates that this
base address register is 32 bits
wide and mapping can be
done anywhere in the 32-bit
memory space.
Memory space indicator. Read
as ZERO, write operations have
no effect. Indicates that this base
address register describes a
memory base address.
Description
Expansion ROM base address
most significant 16 bits. These
bits are written by the host to
specify the location of the Expan-
sion ROM in all of memory
space. ROMBASE must be
written with a valid address
before the PCnet-PCI II control-
ler Expansion ROM access is
enabled by setting ROMEN (PCI
Expansion ROM Base Address
register, bit 0) and MEMEN (PCI
Command register, bit 1).
Since the 16 most significant bits
of the base address areprogram-
mable,
the Expansion ROM on any
64K boundary.
When the PCnet-PCI II controller
is enabled for Expansion ROM
access (ROMEN and MEMEN
are set to ONE), it monitors the
PCI bus for a valid memory com-
mand. If the value on AD[31:2]
during the address phase of the
cycle falls between ROMBASE
and ROMBASE + 64K – 4, the
PCnet-PCI II controller will drive
DEVSEL indicating it will re-
spond to the access.
ROMBASE is read and written by
the host. ROMBASE is cleared
by H_RESET and is not affected
by S_RESET or by setting the
STOP bit.
ROM size. Read as ZEROs,
write operation have no effect.
the
host
can
P R E L I M I N A R Y
map
Am79C970A
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0
PCI Interrupt Line Register (Offset 3Ch)
The PCI Interrupt Line register is an 8-bit register that is
used to communicate the routing of the interrupt. This
register is written by the POST software as it initializes
the PCnet-PCI II controller in the system. The register is
read by the network driver to determine the interrupt
channel which the POST software has assigned to the
PCnet-PCI II controller. The PCI Interrupt Line register
is not modified by the PCnet-PCI II controller. It has no
effect on the operation of the device.
The PCI Interrupt Line register is located at offset 3Ch in
the PCI Configuration Space. It is read and written by
the host. It is cleared by H_RESET and is not affected
S_RESET or by setting the STOP bit.
PCI Interrupt Pin Register (Offset 3Dh)
This PCI Interrupt Pin register is an 8-bit register that in-
dicates the interrupt pin that the PCnet-PCI II controller
is using. The value for the PCnet-PCI II controller Inter-
rupt Pin register is 01h, which corresponds to INTA.
The PCI Interrupt Pin register is located at offset 3Dh in
the PCI Configuration Space. It is read only.
ROMEN
RES
ROMSIZE indicates the maxi-
mum size of the Expansion ROM
the PCnet-PCI II controller can
support. The host can determine
the Expansion ROM size by writ-
ing FFFF F800h to the Expansion
ROM Base Address register. It
will read back a value of ZERO in
bits 15–11, indicating an Expan-
sion ROM size of 64K.
Note that ROMSIZE only speci-
fies the maximum size of Expan-
sion ROM the PCnet-PCI II
controller supports. A smaller
ROM can be used, too. The
actual size of the code in the Ex-
pansion ROM is always deter-
mined by reading the Expansion
ROM header.
Reserved location. Read as
ZEROs, write operations have
no effect.
Expansion ROM enable. Written
by the host to enable access
to the Expansion ROM. The
PCnet-PCI II controller will only
respond to accesses to the Ex-
pansion
ROMEN and MEMEN (PCI Com-
mand register, bit 1) are set
to ONE.
ROMEN is read and written by
the host. ROMEN is cleared by
H_RESET and is not effected by
S_RESET or by setting the
STOP bit.
ROM
when
AMD
both
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