AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 117

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

4
DXMT2PD
in the ring. While performing the
search for the next STP bit that is
set to ONE, the PCnet-PCI II
controller will advance through
the receive descriptor ring re-
gardless of the state of owner-
ship bits. If any of the entries that
are examined during this search
indicate PCnet-PCI II controller
ownership of the descriptor but
also have STP cleared to ZERO,
the PCnet-PCI II controller will
clear the OWN bit to ZERO in
these entries. If a scanned entry
indicates host ownership with
STP cleared to ZERO, the
PCnet-PCI II controller will not al-
ter the entry, but will advance to
the next entry.
When the STP bit is set to ONE,
but the descriptor that contains
this setting is not owned by the
PCnet-PCI II controller, then the
PCnet-PCI II controller will stop
advancing through the ring en-
tries and begin periodic polling of
this entry. When the STP bit is set
to ONE, and the descriptor that
contains this setting is owned by
the PCnet-PCI II controller, then
the PCnet-PCI II controller will
stop advancing through the ring
entries, store the descriptor infor-
mation that it has just read, and
wait for the next receive to arrive.
This behavior allows the host
software to pre-assign buffer
space in such a manner that the
header portion of a receive
packet will always be written to a
particular memory area, and the
data portion of a receive packet
will always be written to a sepa-
rate memory area. The interrupt
is generated when the header
bytes have been written to the
header memory area.
Read/Write accessible always.
LAPPEN
H_RESET or S_RESET and is
not affected by STOP.
See Appendix D for more infor-
mation on the Look Ahead
Packet Processing concept.
Disable Transmit Two Part De-
ferral (see the section “Medium
Allocation” for more details). If
DXMT2PD is set, Transmit Two
Part Deferral will be disabled.
Read/Write accessible always.
DXMT2PD
bit
is
is
cleared
cleared
P R E L I M I N A R Y
Am79C970A
by
by
3
2
1
BSWP
EMBA
RES
H_RESET or S_RESET and is
not affected by STOP.
Enable Modified Back-off Algo-
rithm (see the section “Collision
Handling” for more details). If
EMBA is set, a modified back-off
algorithm is implemented.
Read/Write accessible always.
EMBA is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Byte Swap. This bit is used to
choose between big and little
endian modes of operation.
When BSWP is set to ONE, big
endian mode is selected. When
BSWP is cleared to ZERO, little
endian mode is selected.
When big endian mode is se-
lected, the PCnet-PCI II control-
ler will swap the order of bytes on
the AD bus during a data phase
on accesses to the FIFOs only:
AD[31:24] is byte 0, AD[23:16] is
byte 1, AD[15:8] is byte 2 and
AD[7:0] is byte 3.
When little endian mode is se-
lected, the order of bytes on the
AD bus during a data phase is:
AD[31:24] is byte 3, AD[23:16] is
byte 2, AD[15:8] is byte 1 and
AD[7:0] is byte 0.
Byte swap only affects data
transfers that involve the FIFOs.
Initialization block transfers, de-
scriptor transfers, RDP, RAP,
BDP
space accesses, Address PROM
transfers, and Expansion ROM
accesses are not affected by the
setting of the BSWP bit.
Note that the byte ordering of the
PCI bus is defined to be little
endian. BSWP should not be set
to ONE when the PCnet-PCI II
controller is used in a PCI
bus application.
Read/Write accessible always.
BSWP is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Reserved location. The default
value of this bit is a ZERO. Writ-
ing a ONE to this bit has no effect
on device function. If a ONE is
written to this bit, then a ONE will
be read back. Existing drivers
may write a ONE to this bit for
compatibility, but new drivers
should write a ZERO to this bit
and
PCI
configuration
AMD
117