AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 23

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

INTA
Interrupt Request
An attention signal which indicates that one or more of
the following status flags is set: BABL, EXDINT, IDON,
JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT,
SINT, SLPINT, TINT, TXSTRT and UINT. Each status
flag has either a mask or an enable bit which allows for
suppression of INTA assertion. The flags have the
following meaning:
By default INTA is an open-drain output. For applica-
tions that need a high-active edge sensitive interrupt
signal, the INTA pin can be configured for this mode by
setting INTLEVEL (BCR2, bit 7) to ONE.
When RST is active, INTA is an input for NAND
tree testing.
IRDY
Initiator Ready
IRDY indicates the ability of the initiator of the transac-
tion to complete the current data phase. IRDY is used in
conjunction with TRDY. Wait states are inserted until
both IRDY and TRDY are asserted simultaneously. A
data phase is completed on any clock when both IRDY
and TRDY are asserted.
When the PCnet-PCI II controller is a bus master, it as-
serts IRDY during all write data phases to indicated that
valid data is present on AD[31:0]. During all read data
phases the device asserts IRDY to indicate that it is
ready to accept the data.
When the PCnet-PCI II controller is the target of a trans-
action, it checks IRDY during all write data phases to de-
termine if valid data is present on AD[31:0]. During all
BABL
EXDINT
IDON
JAB
MERR
MISS
MFCO
MPINT
RCVCCO
RINT
SLPINT
SINT
TINT
TXSTRT
UINT
Table 1. Interrupt Flags
Babble
Excessive Deferral
Initialization Done
Jabber
Memory Error
Missed Frame
Missed Frame Count Overflow
Magic Packet Interrupt
Receive Collision Count Overflow
Receive Interrupt
Sleep Interrupt
System Error
Transmit Interrupt
Transmit Start
User Interrupt
Input/Output
Input/Output
P R E L I M I N A R Y
Am79C970A
read data phases the device checks IRDY to determine
if the initiator is ready to accept the data.
When RST is active, IRDY is an input for NAND
tree testing.
LOCK
Lock
In slave mode, LOCK is an input to the PCnet-PCI II con-
troller. A bus master can lock the device to guarantee an
atomic operation that requires multiple transactions.
The PCnet-PCI II controller will never assert LOCK as
a master.
When RST is active, LOCK is an input for NAND
tree testing.
PAR
Parity
Parity is even parity across AD[31:0] and C/BE[3:0].
When the PCnet-PCI II controller is a bus master, it gen-
erates parity during the address and write data phases.
It checks parity during read data phases. When the
PCnet-PCI II controller operates in slave mode, it
checks parity during every address phase. When it is the
target of a cycle, it checks parity during write data
phases and it generates parity during read data phases.
When RST is active, PAR is an input for NAND
tree testing.
PERR
Parity Error
During any slave write transaction and any master read
transaction, the PCnet-PCI II controller asserts PERR
when it detects a data parity error and reporting of the
error is enabled by setting PERREN (PCI Command
register, bit 6) to ONE. During any master write transac-
tion the PCnet-PCI II controller monitors PERR to see if
the target reports a data parity error.
When RST is active, PERR is an input for NAND
tree testing.
REQ
Bus Request
The PCnet-PCI II controller asserts REQ pin as a signal
that it wishes to become a bus master. REQ is driven
high when the PCnet-PCI II controller does not
request the bus.
When RST is active, REQ is an input for NAND
tree testing.
RST
Reset
When RST is asserted low, then the PCnet-PCI II con-
troller performs an internal system reset of the type
Input/Output
Input/Output
Input/Output
AMD
Input
Input
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