AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 54

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

Parity Error Response
During every data phase of a DMA read operation, when
the target indicates that the data is valid by asserting
TRDY, the PCnet-PCI II controller samples the
AD[31:0], C/BE[3:0] and the PAR lines for a data parity
error. When it detects a data parity error, the controller
sets PERR (PCI Status register, bit 15) to ONE. When
reporting of that error is enabled by setting PERREN
(PCI Command register, bit 6) to ONE, the PCnet-PCI II
controller also drives the PERR signal low and sets
DATAPERR (PCI Status register, bit 8) to ONE. The
During every data phase of a DMA write operation, the
PCnet-PCI II controller checks the PERR input to see if
the target reports a parity error. When it sees the PERR
input asserted, the controller sets PERR (PCI Status
register, bit 15) to ONE. When PERREN (PCI Com-
mand register, bit 6) is set to ONE, the PCnet-PCI II con-
troller also sets DATAPERR (PCI Status register, bit 8)
to ONE.
Whenever the PCnet-PCI II controller is the current bus
master and a data parity error occurs, SINT (CSR5, bit
11) will be set to ONE. When SINT is set, INTA is as-
54
AMD
DEVSEL
FRAME
TRDY
PERR
IRDY
C/BE
CLK
PAR
AD
1
DEVSEL is sampled
Figure 23. Master Cycle Data Parity Error Response
2
ADDR
0111
3
P R E L I M I N A R Y
PAR
Am79C970A
4
BE
assertion of PERR follows the corrupted data/byte en-
ables by two clock cycles and PAR by one clock cycle.
The figure below shows a transaction that has a parity
error in the data phase. The PCnet-PCI II controller as-
serts PERR on clock 8, two clock cycles after data is
valid. The data on clock 5 is not checked for parity, since
on a read access PAR is only required to be valid
one clock after the target has asserted TRDY. The
PCnet-PCI II controller then drives PERR high for one
clock cycle, since PERR is a sustained tri-state signal.
serted if the enable bit SINTE (CSR5, bit 10) is set to
ONE. This mechanism can be used to inform the driver
of the system error. The host can read the PCI Status
register to determine the exact cause of the interrupt.
The setting of SINT due to a data parity error is not de-
pendent on the setting of PERREN (PCI Command
register, bit 6).
By default, a data parity error does not affect the state of
the MAC engine. The PCnet-PCI II controller treats the
data in all bus master transfers that have a parity
5
DATA
6
PAR
7
8
9
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