AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 116

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

CSR3: Interrupt Masks and Deferral Control
Bit
31–16 RES
15
14
13
12
11
10
9
8
7
116
AMD
MERRM
BABLM
IDONM
MISSM
RINTM
TINTM
Name
RES
RES
RES
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved location. Read and
written as ZERO.
Babble Mask. If BABLM is set,
the BABL bit will be masked and
unable to set the INTR bit.
Read/Write accessible always.
BABLM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Reserved location. Read and
written as ZERO.
Missed Frame Mask. If MISSM is
set, the MISS bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
MISSM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Memory Error Mask. If MERRM
is set, the MERR bit will be
masked and unable to set the
INTR bit.
Read/Write accessible always.
MERRM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Receive
RINTM is set, the RINT bit will be
masked and unable to set the
INTR bit.
Read/Write accessible always.
RINTM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Transmit
TINTM is set, the TINT bit will be
masked and unable to set the
INTR bit.
Read/Write accessible always.
TINTM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Initialization
IDONM is set, the IDON bit will be
masked and unable to set the
INTR bit.
Read/Write accessible always.
IDONM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Reserved location. Read and
written as ZEROs.
Interrupt
Interrupt
Done
Mask.
Mask.
Mask.
P R E L I M I N A R Y
Am79C970A
If
If
If
6
5
DXSUFLO
LAPPEN
Disable Transmit Stop on Under-
flow error.
When DXSUFLO is cleared to
ZERO, the transmitter is turned
off when an UFLO error occurs
(CSR0, TXON = 0).
When DXSUFLO is set to ONE,
the
gracefully recovers from an
UFLO error. It scans the transmit
descriptor ring until it finds the
start of a new frame and starts a
new transmission.
Read/Write accessible always.
DXSUFLO
H_RESET or S_RESET and is
not affected by STOP.
Look Ahead Packet Processing
Enable. When set to ONE, the
LAPPEN bit will cause the
PCnet-PCI II controller to gener-
ate an interrupt following the de-
scriptor write operation to the first
buffer of a receive frame. This
interrupt will be generated in ad-
dition to the interrupt that is gen-
erated following the descriptor
write operation to the last buffer
of a receive packet. The interrupt
will be signaled through the RINT
bit of CSR0.
Setting LAPPEN to ONE also en-
ables the PCnet-PCI II controller
to read the STP bit of receive de-
scriptors. The PCnet-PCI II con-
troller
information to determine where it
should begin writing a receive
packet’s data. Note that while in
this mode, the PCnet-PCI II con-
troller can write intermediate
packet data to buffers whose
descriptors do not contain STP
bits set to ONE. Following the
write to the last descriptor used
by a packet, the PCnet-PCI II
controller will scan through the
next descriptor entries to locate
the next STP bit that is set to
ONE. The PCnet-PCI II controller
will begin writing the next pack-
et’s data to the buffer pointed to
by that descriptor.
Note that because several de-
scriptors may be allocated by the
host for each packet, and not all
messages may need all of the de-
scriptors
between descriptors that have
STP set to ONE, then some de-
scriptors/buffers may be skipped
PCnet-PCI
will
that
is
use
are
cleared
II
the
controller
allocated
STP
by