AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 95

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

EEPROM MAP
The automatic EEPROM read operation will access 18
words (i.e. 36 bytes) of the EEPROM. The format of the
Note that the first bit out of any word location in the
EEPROM is treated as the MSB of the register that is be-
ing programmed. For example, the first bit out of
EEPROM word location 08h will be written into BCR4,
bit 15, the second bit out of EEPROM word location 08h
will be written into BCR4, bit 14, etc.
There are two checksum locations within the EEPROM.
The first checksum will be used by AMD driver software
to verify that the ISO 8802-3 (IEEE/ANSI 802.3) station
address has not been corrupted. The value of bytes 0Ch
and 0Dh should match the sum of bytes 00h through
0Bh and 0Eh and 0Fh. The second checksum location
— byte 21h — is not a checksum total, but is, instead, a
checksum adjustment. The value of this byte should be
such that the total checksum for the entire 36 bytes of
EEPROM data equals the value FFh. The checksum
EEPROM
Address
address)
(Lowest
Word
0Ah
0Bh
0Ch
0Dh
0Eh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Fh
10h
11h
Addr.
Byte
0Bh
0Dh
1Bh
1Dh
01h
03h
05h
07h
09h
0Fh
11h
13h
15h
17h
19h
1Fh
21h
23h
Second byte of the ISO 8802-3
(IEEE/ANSI 802.3) station physical
address for this node
Fourth byte of the node address
Sixth byte of the node address
Reserved Location: must be 00h
Hardware ID: must be 11h if compatibility
to AMD drivers is desired
User programmable space
MSByte of two-byte checksum, which is the
is the sum of bytes 00h–0Bh and bytes
0Eh and 0Fh
Must be ASCII W (57h) if compatibility to
AMD driver software is desired
BCR4[15:8] (Link Status LED)
BCR5[15:8] (LED1 Status)
BCR18[15:8] (Burst and Bus Control)
BCR2[15:8] (Miscellaneous Configuration)
BCR6[15:8] (LED2 Status)
BCR7[15:8] (LED3 Status)
BCR9[15:8] (Full-Duplex Control)
Checksum adjust byte for the first 36 bytes
of the EEPROM contents, checksum of the
first 36 bytes of the EEPROM should
total to FFh
BCR22[15:8] (PCI Latency)
Reserved location must be 00h
Most Significant Byte
Table 12. EEPROM Content
P R E L I M I N A R Y
Am79C970A
EEPROM contents is shown below, beginning with the
byte that resides at the lowest EEPROM address:
adjust byte is needed by the PCnet-PCI II controller in
order to verify that the EEPROM content has not
been corrupted.
LED Support
The PCnet-PCI II controller can support up to four LEDs.
LED outputs LNKST, LED1 and LED2 allow for direct
connection of an LED and its supporting pullup device.
LED output LED3 may require an additional buffer
between the PCnet-PCI II controller output pin and the
LED and its supporting pullup device.
Because the LED3 output is multiplexed with other
PCnet-PCI II controller functions, it may not always be
possible to connect an LED circuit directly to the LED3
pin. In applications that want to use the pin to drive an
Addr.
Byte
0Ch
1Ch
00h
02h
06h
0Ah
0Eh
10h
12h
14h
16h
18h
1Ah
1Eh
20h
04h
08h
22h
First byte of the ISO 8802-3
(IEEE/ANSI 802.3) station physical
address for this node, where first byte
refers to the first byte to appear on
the 802.3 medium
Third byte of the node address
Fifth byte of the node address
Reserved location must be 00h
Reserved location must be 00h
User programmable space
LSByte of two-byte checksum, which
is the sum of bytes 00h–0Bh and bytes
0Eh and 0Fh
Must be ASCII W (57h) if compatibility to
AMD driver software is desired
BCR4[7:0] (Link Status LED)
BCR5[7:0] (LED1 Status)
BCR18[7:0] (Burst and Bus Control)
BCR2[7:0] (Miscellaneous Configuration)
BCR6[7:0] (LED2 Status)
BCR7[7:0] (LED3 Status)
BCR9[7:0] (Full-Duplex Control)
Reserved location must be 00h
BCR22[7:0] (PCI Latency)
Reserved location must be 00h
Least Significant Byte
AMD
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