M368L3223ETM-CC5 SAMSUNG [Samsung semiconductor], M368L3223ETM-CC5 Datasheet - Page 15

• Manufacturer Part Number: M368L3223ETM-CC5
• Description: 184pin Unbuffered Module based on 256Mb E-die 64/72-bit ECC/Non ECC
• Manufacturer: SAMSUNG [Samsung semiconductor]

c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
d. Evaluation conditions
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns
i. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.
256MB, 512MB DDR466 Unbuffered DIMM
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as:
{1/(Slew Rate1)} - {1/(Slew Rate2)}
would result in the need for an increase in tDS and tDH of 100 ps.
as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.
Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the
voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example : For typical slew rate, DQ0 is switching
Typical
Minimum : 70 °C (T Ambient), VDDQ = 2.5V, slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process
: 25 °C (T Ambient), VDDQ = 2.6V, typical process
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
For Maximum slew rate, only one DQ is switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
Output
Output
Figure 2 : Pulldown slew rate test load
Figure 1 : Pullup slew rate test load
VSSQ
VDDQ
50
50
Ω
Ω
Test point
Test point
Revision 1.0 December, 2003
DDR SDRAM