M368L3223ETM-CC5 SAMSUNG [Samsung semiconductor], M368L3223ETM-CC5 Datasheet - Page 17

• Manufacturer Part Number: M368L3223ETM-CC5
• Description: 184pin Unbuffered Module based on 256Mb E-die 64/72-bit ECC/Non ECC
• Manufacturer: SAMSUNG [Samsung semiconductor]

Command Truth Table
Note : 1. OP Code : Operand Code. A
256MB, 512MB DDR466 Unbuffered DIMM
Register
Register
Refresh
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Burst Stop
Precharge
Active Power Down
Precharge Power Down Mode
DM
No operation (NOP) : Not defined
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
2. EMRS/ MRS can be issued only at all banks precharge state.
3. Auto refresh functions are same as the CBR refresh of DRAM.
4. BA
5. If A
6. During burst write with auto precharge, new read/write command can not be issued.
7. Burst stop command is valid at every burst length.
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
If both BA
If BA
If BA
If both BA
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
A new command can be issued 2 clock cycles after EMRS or MRS.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
0
10
0
0
~ BA
/AP is "High" at row precharge, BA
is "High" and BA
is "Low" and BA
COMMAND
0
0
1
and BA
and BA
: Bank select addresses.
Extended MRS
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
All Banks
1
1
are "Low" at read, write, row active and precharge, bank A is selected.
are "High" at read, write, row active and precharge, bank D is selected.
1
1
is "High" at read, write, row active and precharge, bank C is selected.
is "Low" at read, write, row active and precharge, bank B is selected.
Entry
Entry
Entry
Exit
Exit
Exit
0
~ A
12
& BA
CKEn-1
0
and BA
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
0
~ BA
1
1
CKEn
are ignored and all banks are selected.
: Program keys. (@EMRS/MRS)
H
H
H
H
X
X
L
X
X
X
X
X
L
L
X
RP
CS
after the end of burst.
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
X
H
H
H
H
H
H
X
X
V
X
X
X
V
X
L
L
L
L
L
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
CAS
H
H
H
H
H
H
X
X
V
X
X
X
V
X
L
L
L
L
L
Revision 1.0 December, 2003
WE BA0,1 A10/AP
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
L
V
V
V
X
V
(A0~A9, A11, A12)
OP CODE
OP CODE
H
H
H
Row Address
L
L
L
DDR SDRAM
X
X
X
X
X
X
X
A11, A12
A0 ~ A9
Address
Address
Column
Column
X
Note
1, 2
1, 2
4, 6
3
3
3
3
4
4
4
7
5
8
9
9