IS43DR86400C-25DBLI-TR ISSI, IS43DR86400C-25DBLI-TR Datasheet
IS43DR86400C-25DBLI-TR
Specifications of IS43DR86400C-25DBLI-TR
Related parts for IS43DR86400C-25DBLI-TR
IS43DR86400C-25DBLI-TR Summary of contents
Page 1
... Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products ...
Page 2
... DMa - DMb = DM; DQSa - DQSb = DQS; DQSa - DQSb = DQS; RDQS, RDQS available only for x8 4. For x16 devices: DMa - DMb = UDM, LDM; DQSa - DQSb = UDQS, LDQS; DQSa - DQSb = UDQS, LDQS 2 Integrated Silicon Solution, Inc. — www.issi.com DMa - DMb RDQS, RDQS Rev. A 3/19/2013 ...
Page 3
... Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank precharged, the bank is selected by BA0 - BA1. The address inputs also provide the op-code during MRS or EMRS commands. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 ...
Page 4
... No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.8 V +/- 0.1 V VSSQ Supply DQ Ground VDDL Supply DLL Power Supply: 1.8 V +/- 0.1 V VSSDL Supply DLL Ground VDD Supply Power Supply: 1.8 V +/- 0.1 V VSS Supply Ground VREF Supply Reference voltage 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 ...
Page 5
... Chip select /RAS, /CAS, /WE Command input CKE Clock enable CK, /CK Differential clock input DM Write data mask RDQS, /RDQS Differential Redundant Data Strobe Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 VDD RDQS VSSQ VSS DQ6 VSSQ DQS ...
Page 6
... Supply voltage for DQ circuit VSSQ Ground for DQ circuit VREF Input reference voltage VDDL Supply voltage for DLL circuit VSSDL Ground for DLL circuit NC No connection Integrated Silicon Solution, Inc. — www.issi.com VDDQ UDQS DQ15 VSSQ VDDQ DQ8 DQ13 VSSQ VDDQ LDQS ...
Page 7
... Peak to peak ac noise on VREF may not exceed +/-2 % VREF(dc). 4. VTT of transmitting device must track VREF of receiving device. 5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDL tied together Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 ...
Page 8
... T = - -40 to +105 -40 to +105 a Theta-ja Theta-ja (Airflow = 1m/s) 35.8 32.0 33.9 30.3 SYMBOL R 1(eff) tt 2(eff 3(eff) tt ΔVM Integrated Silicon Solution, Inc. — www.issi.com Units Theta-ja Theta-jc (Airflow = 2m/s) 29.8 5.9 28.3 5.7 MIN NOM MAX UNITS NOTES Ω Ω ...
Page 9
... VIL(ac) max for falling edges as shown in the below figure timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. AC input test signal waveform V SWING(MAX) Falling Slew = Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 Min. Max. VREF + 0.125 VDDQ + 0 ...
Page 10
... VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross. 10 Min. Max. 0.5 VDDQ 0.5 x VDDQ - 0.175 0.5 x VDDQ + 0.175 V DDQ Crossing point SSQ Min. Max. 0.5 x VDDQ - 0.125 0.5 x VDDQ + 0.125 Integrated Silicon Solution, Inc. — www.issi.com Units Notes V 1 Units Notes V 1 Rev. A 3/19/2013 ...
Page 11
... Maximum overshoot area above VDDQ (See Figure below) Maximum undershoot area below VSSQ (See Figure below) Maximum Amplitude V DDQ Volts V SSQ (V) Maximum Amplitude AC overshoot and undershoot definition for clock, data, strobe, and mask pins Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 Specification DDR2-400 DDR2-533 0.5V 0.5V 0.5V 0.5V 1.33 V-ns 1 ...
Page 12
... DDR2 SDRAM output slew rate test load is defined in General Note 3 of the AC Timing specification Table. 12 SSTL_18 0.5 x VDDQ SSTL_18 Units Notes - 13 13 Min Nom Max Unit Notes Ω See full strength default 1 driver characteristics Ω 0 1.5 6 Ω 1,2,3 1.5 5 V/ns 1,4,5,7,8,9 Integrated Silicon Solution, Inc. — www.issi.com Units Notes V 1 Rev. A 3/19/2013 ...
Page 13
... Operating burst write current; All banks open, Continuous burst writes CL(IDD tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 -25D/-25E -3D DDR2- DDR2- ...
Page 14
... The -25E, -37C, and-5B device specifications are shown for reference only. 14 -25D/-25E -3D -37C DDR2- DDR2- DDR2- 800D/800E 667D 533C 345 275 230 230 185 175 370 350 340 Integrated Silicon Solution, Inc. — www.issi.com -5B Units DDR2- 400B 190 mA 170 265 mA Rev. A 3/19/2013 ...
Page 15
... Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 Units 5-5-5 5 tCK 15 ns ...
Page 16
... C < Tc ≤ 105 oper may not be violated. oper -25E -3D DDR2-800E DDR2-667D DDR2-533C 6-6-6 5-5 3.75 3. 2.5 – Integrated Silicon Solution, Inc. — www.issi.com Units Notes 105 7.8 1 3.9 1 3.9 1,2,3 may not be violated. -37C -5B DDR2-400B 4-4-4 3-3 ...
Page 17
... DQS(DQS) low-impedance time from CK low-impedance time from CK/ CK DQS-DQ skew for DQS and associated DQ signals CK half pulse width DQ hold skew factor DQ/DQS output hold time from DQS Read preamble Read postamble Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 DDR2-400 Symbol Min. Max. tCK ...
Page 18
... Integrated Silicon Solution, Inc. — www.issi.com DDR2-533 Units Min. Max. 7.5 – – 2 – tCK 15 – tRP – tCK 7.5 – ns 7.5 – – ...
Page 19
... DQS/DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals CK half pulse width DQ hold skew factor DQ/DQS output hold time from DQS Read preamble Read postamble Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 DDR2-667 Symbol Min. Max. tCK(avg) 3 ...
Page 20
... Integrated Silicon Solution, Inc. — www.issi.com DDR2-800 Units Notes Min. Max. 7.5 – ns 4,32 10 – 2 – nCK 15 – – nCK 33 tnRP 7.5 – ...
Page 21
... It is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ DQ ...
Page 22
... Specific Notes on derating for other slew rate values DQSL t WPST V (dc (dc (ac) (dc DMin DMin DMin V V (ac) (dc DQSQmax t DQSQmax t QH Integrated Silicon Solution, Inc. — www.issi.com t RPST 3/19/2013 Rev. A ...
Page 23
... Slew 1 rate 1 V/ns 0 - DDR2-667/800 tDS/tDH derating with differential data strobe Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 , DQS, DQS Differential Slew Rate 2.0 V/ns 1.8 V/ns 1.6 V/ns 125 -11 - -25 -31 -13 - -31 ...
Page 24
... Integrated Silicon Solution, Inc. — www.issi.com 0.7 V/ns 0.6 V/ns 0.5 V/ -29 - -43 -62 -60 - -61 -85 -78 -109 -108 -152 -85 -114 -102 -138 -132 -181 -183 -246 -128 -156 -145 -180 -175 -223 -226 -288 - - -210 -243 -240 -286 -291 -351 ...
Page 25
... Command/ 0.8 -25 Address Slew rate 0.7 -43 (V/ns) 0.6 -67 0.5 -110 0.4 -175 0.3 -285 0.25 -350 0.2 -525 0.15 -800 0.1 -1450 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 CK, /CK Differential Slew Rate 2.0 V/ns 1.5 V/ns DtIH DtIS DtIH 94 217 124 89 209 119 83 197 113 75 180 105 45 155 75 21 113 ...
Page 26
... Integrated Silicon Solution, Inc. — www.issi.com 1.0 V/ns Units Notes DtIH 154 ps 1 149 ps 1 143 ps 1 135 ps 1 105 ...
Page 27
... One method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 ...
Page 28
... This means: For DDR2-667 5-5-5, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15ns due to input clock jitter. 28 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 ...
Page 29
... Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across n cycles ... 10, inclusive Cumulative error across n cycles ... 50, inclusive Duty cycle jitter Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 Symbol DDR2-667 DDR2-800 min max min ...
Page 30
... Integrated Silicon Solution, Inc. — www.issi.com max Units tCK(avg),max + tJIT(per),max tJIT(duty),max tJIT(duty),max Rev ...
Page 31
... However tAC values used in the equations shown above are from the timing parameter table and are not derated. Thus the final derated values for tAOF are; tAOF,min(derated_final) = tAOF,min(derated tJIT(duty),max - tERR(6-10per),max } tAOF,max(derated_final) = tAOF,max(derated tJIT(duty),min - tERR(6-10per),min } Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 31 ...
Page 32
... DC operating conditions" (SSTL_1.8)) and stable clock (CK, CK), then apply NOP or Deselect & take CKE HIGH. d) Wait minimum of 400ns then issue precharge all command. NOP or Deselect applied during 400 ns period. e) Issue an EMRS command to EMR(2). 32 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 ...
Page 33
... EMR(2), or EMR(3) variables, all variables within the addressed register must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and Reset DLL do not affect memory array contents, which means re-initialization including those can be executed at any time after power-up without affecting memory array contents. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 PRE ...
Page 34
... mode bit and must be set to LOW for normal MRS operation used for DLL reset. Write recovery time WR is defined A11. Refer to the table for specific codes. 34 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 ...
Page 35
... RU{ tWR[ns] / tCK(avg)[ns] }, where RU stands for round up. The mode register must be programmed to this value. This is also used with tRP to determine tDAL. 2. Speed bin determined. Refer to Key Timing Parameter table. 3. A13, only applicable for x8. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 Active power down exit time ...
Page 36
... Integrated Silicon Solution, Inc. — www.issi.com Interleave Addressing (decimal Interleave Addressing (decimal) ...
Page 37
... Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 ...
Page 38
... Reserved Reserved 1 1 Output Drive Impedance Control Full Strength Reduced strength Integrated Silicon Solution, Inc. — www.issi.com Strobe Function Marix A10 (/DQS) RDQS/DM /RDQS DQS 0 DQS DM Hi Hi-z DQS 0 RDQS /RDQS DQS 1 RDQS Hi-z DQS ...
Page 39
... If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued. 4. A13 is only applicable for x8. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 ...
Page 40
... All bits in EMR(3) except BA0 and BA1 are reserved for future use and must be set to 0 when programming this mode register. Address Field BA1 BA0 A13 A12 A11 Mode Register A10 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 ...
Page 41
... L (but a defined logic level)” 7. Self refresh exit is asynchronous. 8. VREF must be maintained during Self Refresh operation. 9. BAx and Axx refers to the MSBs of bank addresses and addresses, respectively. 10. For x16 option, A13 is "Don't Care" (X) for Activate. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 BA1 - CS ...
Page 42
... L DESELECT or NOP L REFRESH H Refer to the Command Truth Table DQs Note Valid Integrated Silicon Solution, Inc. — www.issi.com Action (N) Notes 3 Maintain Power-Down 11, 13, 15 Power Down Exit 4, 8, 11, 13 Maintain Self Refresh 11, 15,16 Self Refresh Exit Active Power Down Entry 4, 8, 10, 11, 13 ...
Page 43
... Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 43 ...
Page 44
... Self Refresh mode. ODT timing diagrams follow for Active/Standby mode and Power Down mode. EMRS to ODT Update Delay CMD E MRS CK CK ODT tAOFD tMOD,min Rtt Old setting 44 NOP NOP NOP tMOD,max ODT Ready Integrated Silicon Solution, Inc. — www.issi.com NOP NOP tIS tAOND Updated Rev. A 3/19/2013 ...
Page 45
... V (ac) ODT IH t AOND ODT On/Off Timing for Power-Down mode CKE ODT (ac AONPD,min t AONPD,max Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 (ac) t AOFD IL Valid t AOF,min t AON,min t AON,max (ac) ...
Page 46
... Please contact ISSI for availability of leaded options. 2. The -3D, and -25D speed options are backward compatible with all the timing specifications for slower grades - + IS43DR86400C-25DBLI 5-5-5 IS43DR86400C-25DBI 5-5-5 IS43DR86400C-3DBLI 5-5-5 IS46DR86400C-3DBLA1 C o 5-5-5 IS43DR16320C-25DBL ...
Page 47
... IS43/46DR86400C, IS43/46DR16320C Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 47 ...
Page 48
... IS43/46DR86400C, IS43/46DR16320C 48 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 3/19/2013 ...