IS43DR86400C-25DBLI-TR ISSI, IS43DR86400C-25DBLI-TR Datasheet - Page 35

• Manufacturer Part Number: IS43DR86400C-25DBLI-TR
• Description: DRAM 512M, 1.8V, 400Mhz 64Mx8 DDR2
• Manufacturer: ISSI

Specifications of IS43DR86400C-25DBLI-TR

• Rohs: yes
• Data Bus Width: 8 bit
• Organization: 64 M x 8
• Package / Case: BGA-60
• Memory Size: 512 Mbit
• Maximum Clock Frequency: 400 MHz
• Access Time: 400 ps
• Supply Voltage - Max: 1.9 V
• Supply Voltage - Min: 1.7 V
• Maximum Operating Current: 135 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46DR86400C, IS43/46DR16320C
DDR2 SDRAM Mode Register Set (MRS)
Notes:
1. For DDR2-400/533, WR (write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock
2. Speed bin determined. Refer to Key Timing Parameter table.
3. A13, only applicable for x8.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
3/19/2013
Address
cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR[cycles] = RU{ tWR[ns] / tCK[ns] }, where RU
stands for round up). For DDR2-667/800, WR min is determined by tCK(avg) max and WR max is determined by tCK(avg) min. WR[cycles] =
RU{ tWR[ns] / tCK(avg)[ns] }, where RU stands for round up. The mode register must be programmed to this value. This is also used with tRP
to determine tDAL.
Field
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Latency
Register
Length
CAS
Burst
Mode
WR
DLL
TM
BT
PD
0
0
0
A12
A11
A8
A6
A3
0
1
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
1
A10
Active power down exit time
A5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Slow exit(use tXARDS)
Fast exit (use tXARD)
Burst Type
DLL Reset
Sequential
Interleave
Yes
No
A9
A4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
WR(cycles)
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
4
5
6
5
6
3
4
2
2
2
2
*1
A7
A2
0
1
0
0
A1
1
1
Reserved
Normal
Mode
A0
0
1
BL
4
8
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