IS43DR86400C-25DBLI-TR ISSI, IS43DR86400C-25DBLI-TR Datasheet - Page 29

• Manufacturer Part Number: IS43DR86400C-25DBLI-TR
• Description: DRAM 512M, 1.8V, 400Mhz 64Mx8 DDR2
• Manufacturer: ISSI

Specifications of IS43DR86400C-25DBLI-TR

• Rohs: yes
• Data Bus Width: 8 bit
• Organization: 64 M x 8
• Package / Case: BGA-60
• Memory Size: 512 Mbit
• Maximum Clock Frequency: 400 MHz
• Access Time: 400 ps
• Supply Voltage - Max: 1.9 V
• Supply Voltage - Min: 1.7 V
• Maximum Operating Current: 135 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46DR86400C, IS43/46DR16320C
33. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed
in the mode register set.
34. New units, ‘tCK(avg)’ and ‘nCK’, are introduced in DDR2-667 and DDR2-800.
Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation.
Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
Note that in DDR2-400 and DDR2-533, ‘tCK’ is used for both concepts.
ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2,
even if (Tm+2 - Tm) is 2 x tCK(avg) + tERR(2per),min.
35. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock
jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random
jitter meeting a Gaussian distribution.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
3/19/2013
Parameter
Clock period jitter
Clock period jitter during DLL locking
period
Cycle to cycle clock period jitter
Cycle to cycle clock period jitter during
DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across n cycles, n = 6 ...
10, inclusive
Cumulative error across n cycles, n = 11
... 50, inclusive
Duty cycle jitter
Symbol
tJIT(per)
tJIT(per,lck)
tJIT(cc
tJIT(cc,lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6-
10per)
tERR(11-
50per)
tJIT(duty)
-125
-100
-250
-200
-175
-225
-250
-250
-350
-450
-125
min
DDR2-667
max
125
100
250
200
175
225
250
250
350
450
125
-100
-200
-160
-150
-175
-200
-200
-300
-450
-100
min
-80
DDR2-800
max
100
200
160
150
175
200
200
300
450
100
80
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Notes
35
35
35
35
35
35
35
35
35
35
35
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