IS43DR86400C-25DBLI-TR ISSI, IS43DR86400C-25DBLI-TR Datasheet - Page 2

• Manufacturer Part Number: IS43DR86400C-25DBLI-TR
• Description: DRAM 512M, 1.8V, 400Mhz 64Mx8 DDR2
• Manufacturer: ISSI

Specifications of IS43DR86400C-25DBLI-TR

• Rohs: yes
• Data Bus Width: 8 bit
• Organization: 64 M x 8
• Package / Case: BGA-60
• Memory Size: 512 Mbit
• Maximum Clock Frequency: 400 MHz
• Access Time: 400 ps
• Supply Voltage - Max: 1.9 V
• Supply Voltage - Min: 1.7 V
• Maximum Operating Current: 135 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46DR86400C, IS43/46DR16320C
GENERAL DESCRIPTION
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue
for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the active
command are used to select the bank and row to be accessed (BA0-BA1 select the bank; A0-A12(x16) or A0-A13(x8)
select the row). The address bits registered coincident with the Read or Write command are used to select the starting
column location A0-A9 for the burst access and to determine if the auto precharge A10 command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command descriptions and device operation.
FUNCTIONAL BLOCK DIAGRAM
2
Notes:
1. An:n = no. of address pins - 1
2. DQm: m = no. of data pins - 1
3. For x8 devices:
DMa - DMb = DM; DQSa - DQSb = DQS; DQSa - DQSb = DQS; RDQS, RDQS available only for x8
4. For x16 devices:
DMa - DMb = UDM, LDM; DQSa - DQSb = UDQS, LDQS; DQSa - DQSb = UDQS, LDQS
Integrated Silicon Solution, Inc. — www.issi.com
RDQS, RDQS
DMa - DMb
3/19/2013
Rev. A