C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 180

• Manufacturer Part Number: C8051F961-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
• Manufacturer: Silicon Labs

Specifications of C8051F961-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-40
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 34
• Number Of Timers: 4

C8051F96x
14.2.1. Key Inversion using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power con-
sumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use with the code examples. The steps are documented in the datasheet for complete-
ness.
Steps to generate the Decryption Key from Encryption Key
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180
Prepare encryption key and dummy data in xram.
Reset AES module by clearing bit 3 of AES0BCFG.
Disable the first three DMA channels by clearing bits 0 to 2 in the DMA0EN sfr.
Configure the first DMA channel for the AES0KIN sfr.
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Configure the second DMA channel for the AES0BIN sfr.
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Configure the third DMA channel for the AES0YOUT sfr.
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Clear first three DMA interrupts by clearing bits 0 to 2 in the DMA0INT sfr.
Enable first three DMA channels setting bits 0 to 2 in the DMA0EN sfr
Configure the AES Module data flow for inverse key generation by writing 0x04 to the AES0DCFG sfr.
Write key size to bits 1 and 0 of the AES0BCFG.
Configure the AES core for encryption by setting the bit 2 of AES0BCFG.
Initiate the encryption operation by setting bit 3 of AES0BCFG.
Wait on the DMA interrupt from DMA channel 2.
Disable the AES Module by clearing bit 2 of AES0BCFG.
Disable the DMA by writing 0x00 to DMA0EN.
Select the first DMA channel by writing 0x00 to the DMA0SEL sfr.
Configure the first DMA channel to move xram to AES0KIN sfr by writing 0x05 to the DMA0NCF sfr.
Clear DMA0NMD to disable wrapping.
Write the xram address of the encryption key to the DMA0NBAH and DMA0NBAL sfrs.
Write the key length in bytes to DMA0NSZL sfr.
Clear DMA0NSZH
Clear DMA0NAOH and DMA0NAOL.
Select the second DMA channel by writing 0x01 to the DMA0SEL sfr.
Configure the second DMA channel to move xram to AES0BIN sfr by writing 0x06 to the DMA0NCF sfr.
Clear DMA0NMD to disable wrapping.
Write the xram address of dummy data to the DMA0NBAH and DMA0NBAL sfrs.
Write 0x10 (16) to the DMA0NSZL sfr.
Clear DMA0NSZH
Clear DMA0NAOH and DMA0NAOL
Select the third DMA channel by writing 0x02 to the DMA0SEL sfr.
Configure the third DMA channel to move the contents of the AES0YOUT sfr to xram by writing 0x08 to the
DMA0NCF sfr.
Enable transfer complete interrupt by setting bit 7 of DMA0NCF sfr.
Clear DMA0NMD to disable wrapping.
Write the xram address for the decryption key to the DMA0NBAH and DMA0NBAL sfrs.
Write the key length in bytes to DMA0NSZL sfr.
Clear DMA0NSZH.
Clear DMA0NAOH and DMA0NAOL.
Rev. 0.5