C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 83

• Manufacturer Part Number: C8051F961-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
• Manufacturer: Silicon Labs

Specifications of C8051F961-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-40
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 34
• Number Of Timers: 4

5.2.4. Settling Time Requirements
A minimum amount of tracking time is required before each conversion can be performed, to allow the
sampling capacitor voltage to settle. This tracking time is determined by the AMUX0 resistance, the ADC0
sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note
that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion.
For many applications, these three SAR clocks will meet the minimum tracking time requirements, and
higher values for the external source impedance will increase the required tracking time.
Figure 5.4 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation . When measuring the Temperature Sensor output or
V
requirements as well as the mux impedance and sampling capacitor values.
ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
n is the ADC resolution in bits (10).
5.2.5. Gain Setting
The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined
directly by V
The 0.5x gain setting can be useful to obtain a higher input Voltage range when using a small V
age, or to measure input voltages that are between V
trolled by the AMP0GN bit in register ADC0CF.
DD
TOTAL
with respect to GND, R
is the sum of the AMUX0 resistance and any external source resistance.
REF
Note: The value of CSAMPLE depends on the PGA Gain. See Table 4.12 for details.
. In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is V
Figure 5.4. ADC0 Equivalent Input Circuits
P0.x
TOTAL
t
=
reduces to R
RC
ln
MUX Select
Input


------ -
SA
2
= R
n


MUX

Rev. 0.5
R
* C
MUX
TOTAL
R
MUX
SAMPLE
. See Table 4.12 for ADC0 minimum settling time
REF
C
and V
SAMPLE
DD
. Gain settings for the ADC are con-
C
SAMPLE
C8051F96x
REF
REF
volt-
x 2.
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