C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 196

• Manufacturer Part Number: C8051F961-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
• Manufacturer: Silicon Labs

Specifications of C8051F961-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-40
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 34
• Number Of Timers: 4

C8051F96x
14.6.4.1. CBC Decryption using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power con-
sumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use with the code examples. The steps are documented in the datasheet for complete-
ness.
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196
Prepare decryption Key, initialization vector, and data to be decrypted in xram.
The initialization vector should be located immediately before the data to be decrypted to decrypt
multiple blocks.
Reset AES module by clearing bit 2 of AES0BCFG.
Disable the first four DMA channels by clearing bits 0 to 3 in the DMA0EN sfr.
Configure the first DMA channel for the AES0KIN sfr
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Configure the second DMA channel for the AES0BIN sfr.
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Configure the third DMA channel for the AES0XIN sfr.
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Configure the forth DMA channel for the AES0YOUT sfr
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Clear first four DMA interrupts by clearing bits 0 to 2 in the DMA0INT sfr.
Enable first four DMA channels setting bits 0 to 2 in the DMA0EN sfr
Configure the AES Module data flow for XOR on output data by writing 0x02 to the AES0DCFG sfr.
Write key size to bits 1 and 0 of the AES0BCFG
Configure the AES core for decryption by clearing bit 2 of AES0BCFG
Initiate the decryption operation be setting bit 3 of AES0BCFG
Wait on the DMA interrupt from DMA channel 3
Disable the AES Module by clearing bit 2 of AES0BCFG
Disable the DMA by writing 0x00 to DMA0EN
Select the first DMA channel by writing 0x00 to the DMA0SEL sfr
Configure the first DMA channel to move xram to AES0KIN sfr by writing 0x05 to the DMA0NCF sfr
Write 0x01 to DMA0NMD to enable wrapping
Write the xram location of decryption key to the DMA0NBAH and DMA0NBAL sfrs.
Write the key length in bytes to DMA0NSZL sfr
Clear the DMA0NSZH sfr
Clear the DMA0NAOH and DMA0NAOL sfrs
Select the second DMA channel by writing 0x01 to the DMA0SEL sfr.
Configure the second DMA channel to move xram to AES0BIN sfr by writing 0x06 to the DMA0NCF sfr.
Clear DMA0NMD to disable wrapping.
Write the xram address of the data to be decrypted to the DMA0NBAH and DMA0NBAL sfrs.
Write the number of bytes to be decrypted in multiples of 16 bytes to the DMA0NSZH and DMA0NSZL sfrs.
Clear the DMA0NAOH and DMA0NAOL sfrs.
Select the third DMA channel by writing 0x02 to the DMA0SEL sfr.
Configure the third DMA channel to move xram to AES0XIN sfr by writing 0x07 to the DMA0NCF sfr.
Clear DMA0NMD to disable wrapping.
Write the xram address of initialization vector to the DMA0NBAH and DMA0NBAL sfrs.
Write the number of bytes to be decrypted in multiples of 16 bytes to the DMA0NSZH and DMA0NSZL sfrs.
Clear the DMA0NAOH and DMA0NAOL sfrs.
Select the forth channel by writing 0x03 to the DMA0SEL sfr
Configure the forth DMA channel to move the contents of the AES0YOUT sfr to xram by writing 0x08 to the
DMA0NCF sfr
Enable transfer complete interrupt by setting bit 7 of DMA0NCF sfr
Clear DMA0NMD to disable wrapping
Write the xram address for decrypted data to the DMA0NBAH and DMA0NBAL sfrs.
Write the number of bytes to be decrypted in multiples of 16 bytes to the DMA0NSZH and DMA0NSZL sfrs.
Clear the DMA0NAOH and DMA0NAOL sfrs.
Rev. 0.5