C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 192

• Manufacturer Part Number: C8051F961-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
• Manufacturer: Silicon Labs

Specifications of C8051F961-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-40
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 34
• Number Of Timers: 4

C8051F96x
14.6.2. CBC Encryption Initialization Vector Location
The first block to be encrypted uses the initialization vector for the AES0XIN data. Subsequent blocks will
use the encrypted ciphertext from the previous block. The DMA is capable of encrypting multiple bocks. If
the initialization is located at an arbitrary location in xram, the DMA base address location will need to be
changed to the start of the encrypted ciphertext after encrypting the first block. However, if the initialization
vector explicitly located in xram immediately before the encrypted ciphertext, the pointer will be advanced
to the start of the encrypted ciphertext naturally and multiple blocks can be encrypted autonomously.
14.6.3. CBC Encryption using DMA
Normally, the AES block is used with the DMA. This provides the best performance and lowest power con-
sumption. Code examples are provided in 8051 compiler independent C code using the DMA. It is highly
recommended to use with the code examples. The steps are documented in the datasheet for complete-
ness.
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(The initialization vector should be located immediately before the data to be encrypted to encrypt multiple
blocks.)
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192
Prepare encryption Key, initialization vector, and data to be encrypted in xram.
Reset AES module by clearing bit 2 of AES0BCFG.
Disable the first four DMA channels by clearing bits 0 to 3 in the DMA0EN sfr.
Configure the first DMA channel for the AES0KIN sfr
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Configure the second DMA channel for the AES0BIN sfr.
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Configure the third DMA channel for the AES0XIN sfr.
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* Configure the forth DMA channel for the AES0YOUT sfr
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Clear first four DMA interrupts by clearing bits 0 to 2 in the DMA0INT sfr.
Select the first DMA channel by writing 0x00 to the DMA0SEL sfr
Configure the first DMA channel to move xram to AES0KIN sfr by writing 0x05 to the DMA0NCF sfr
Write 0x01 to DMA0NMD to enable wrapping
Write the xram location of encryption key to the DMA0NBAH and DMA0NBAL sfrs.
Write the key length in bytes to DMA0NSZL sfr
Clear the DMA0NSZH sfr
Clear the DMA0NAOH and DMA0NAOL sfrs
Select the second DMA channel by writing 0x01 to the DMA0SEL sfr.
Configure the second DMA channel to move xram to AES0BIN sfr by writing 0x06 to the DMA0NCF sfr.
Clear DMA0NMD to disable wrapping.
Write the xram address of the data to be encrypted to the DMA0NBAH and DMA0NBAL sfrs.
Write the number of bytes to be encrypted in multiples of 16 bytes to the DMA0NSZH and DMA0NSZL sfrs.
Clear the DMA0NAOH and DMA0NAOL sfrs.
Select the third DMA channel by writing 0x02 to the DMA0SEL sfr.
Configure the third DMA channel to move xram to AES0XIN sfr by writing 0x07 to the DMA0NCF sfr.
Clear DMA0NMD to disable wrapping.
Write the xram address of initialization vector to the DMA0NBAH and DMA0NBAL sfrs.
Write the number of bytes to be encrypted in multiples of 16 bytes to the DMA0NSZH and DMA0NSZL sfrs.
Clear the DMA0NAOH and DMA0NAOL sfrs.
Select the forth channel by writing 0x03 to the DMA0SEL sfr
Configure the forth DMA channel to move the contents of the AES0YOUT sfr to xram by writing 0x08 to the
DMA0NCF sfr
Enable transfer complete interrupt by setting bit 7 of DMA0NCF sfr
Clear DMA0NMD to disable wrapping
Write the xram address for encrypted data to the DMA0NBAH and DMA0NBAL sfrs.
Write the number of bytes to be encrypted in multiples of 16 bytes to the DMA0NSZH and DMA0NSZL sfrs.
Clear the DMA0NAOH and DMA0NAOL sfrs.
Rev. 0.5