C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 263

• Manufacturer Part Number: C8051F961-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
• Manufacturer: Silicon Labs

Specifications of C8051F961-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-40
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 34
• Number Of Timers: 4

19.5. Suspend Mode
Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal
oscillators disabled. The system clock source must be set to the low power internal oscillator or the preci-
sion oscillator prior to entering Suspend Mode. All digital logic (timers, communication peripherals, inter-
rupts, CPU, etc.) stops functioning until one of the enabled wake-up sources occurs.
The following wake-up sources can be configured to wake the device from Suspend Mode:
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Note: Upon wake-up from suspend mode, PMU0 requires two system clocks in order to update the PMU0CF wake-
In addition, a noise glitch on RST that is not long enough to reset the device will cause the device to exit
suspend. In order for the MCU to respond to the pin reset event, software must not place the device back
into suspend mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-
up was due to a falling edge on the /RST pin. If the wake-up source is not due to a falling edge on RST,
there is no time restriction on how soon software may place the device back into suspend mode. A 4.7 kW
pullup resistor to VDD is recommend for RST to prevent noise glitches from waking the device.
19.6. Sleep Mode
Setting the Sleep Mode Select bit (PMU0CF.7) turns off the internal 1.8 V regulator (VREG0) and switches
the power supply of all on-chip RAM to the VBAT pin (see Figure 19.1). Power to most digital logic on the
chip is disconnected; only PMU0, LCD, Power Select Switch, Pulse Counter, and the SmaRTClock remain
powered. Analog peripherals remain powered; however, only the Comparators remain functional when the
device enters Sleep Mode. All other analog peripherals (ADC0, IREF0, External Oscillator, etc.) should be
disabled prior to entering Sleep Mode. The system clock source must be set to the low power internal
oscillator or the precision oscillator prior to entering Sleep Mode.
GPIO pins configured as digital outputs will retain their output state during sleep mode. In two-cell mode,
they will maintain the same current drive capability in sleep mode as they have in normal mode.
GPIO pins configured as digital inputs can be used during sleep mode as wakeup sources using the port
match feature. In two-cell mode, they will maintain the same input level specs in sleep mode as they have
in normal mode.
‘C8051F96x devices support a wakeup request for external devices. Upon exit from sleep mode, the wake-
up request signal is driven low, allowing other devices in the system to wake up from their low power
modes.
RAM and SFR register contents are preserved in sleep mode as long as the voltage on VBAT does not fall
below V
resume code execution upon waking up from Sleep mode.
Pulse Counter Count Reached Event
VBAT Monitor (part of LCD logic)
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge
up flags. All flags will read back a value of '0' during the first two system clocks following a wake-up from
suspend mode.
POR
. The PC counter and all other volatile state information is preserved allowing the device to
Rev. 0.5
C8051F96x
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