MK40DN512VMD10 Freescale Semiconductor, MK40DN512VMD10 Datasheet - Page 60

• Manufacturer Part Number: MK40DN512VMD10
• Description: ARM Microcontrollers - MCU KINETIS 512K USB LCD
• Manufacturer: Freescale Semiconductor

Specifications of MK40DN512VMD10

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: K40
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 100 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: MAPBGA-144
• Mounting Style: SMD/SMT

Peripheral operating requirements and behaviors
6.8.6 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
60
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
range the maximum frequency of operation is reduced.
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
Num
Operating voltage
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DSPI_SCK to DSPI_PCSn invalid delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Operating voltage
Frequency of operation
Table 42. Master mode DSPI timing (full voltage range)
Table 43. Slave mode DSPI timing (full voltage range)
Figure 22. DSPI classic SPI timing — master mode
DS7
DS3
Description
K40 Sub-Family Data Sheet, Rev. 2, 12/2012.
First data
Description
DS8
First data
Table continues on the next page...
DS5
DS2
Data
Data
DS6
(t
(t
(t
BUS
BUS
SCK
4 x t
DS1
Last data
1.71
19.1
Min.
-1.2
—
—
/2) - 4
4
4
0
x 2) −
x 2) −
BUS
Last data
1.71
Min.
—
(t
DS4
SCK/2)
Max.
12.5
3.6
8.5
—
—
—
—
—
—
+ 4
Freescale Semiconductor, Inc.
Max.
6.25
3.6
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
MHz
Notes
Unit
V
1
2
3