MPXN2120VMG116 Freescale Semiconductor, MPXN2120VMG116 Datasheet - Page 39

• Manufacturer Part Number: MPXN2120VMG116
• Description: Microprocessors - MPU 32BIT2M NVM GATEWAY
• Manufacturer: Freescale Semiconductor

Specifications of MPXN2120VMG116

• Rohs: yes
• Processor Series: PXN21
• Core: e200
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 60 MHz
• Program Memory Size: 2 MB
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SPI, UART
• Operating Supply Voltage: - 0.3 V to + 1.32 V
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-208
• Number Of Programmable I/os: 155

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4.11
1
4.12
Freescale Semiconductor
Spec
Spec
The maximum frequency value is with frequency modulation disabled. If frequency modulation is enabled, the maximum
frequency value should be de-rated by the percentage of modulation enabled so that the maximum frequency is not exceeded.
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.
This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal
startup time.
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C
Modulation depth selected must not result in f
Maximum and minimum variations from programmed modulation depth are 2%, 3%, and 4% peak-to-peak. Use only these
settings.
Depth tolerance is the programmed modulation depth ±0.25% of f
See the Block Guide for VCO frequency synthesis equations.
Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than
1 MHz will result in reduced calibration accuracy.
TUE assumes no pin activity on pins adjacent to analog channel or output driver activity on corresponding V
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11
1
2
3
4
5
1
2
3
4
5
6
7
8
9
Double Word (64 bits) Program Time
Page (128 bits and 256 bits) Program Time
16 KB Block Pre-program and Erase Time
64 KB Block Pre-program and Erase Time
128 KB Block Pre-program and Erase Time
Analog High Reference Voltage
Analog Low Reference Voltage
Analog Input Voltage
Sampling Frequency
Maximum ADC Clock Frequency
Sampling Time
Differential Non Linearity
Integral Non Linearity
Offset Error
Gain Error
Total Unadjusted Error
V
V
ADC electrical characteristics
Flash memory electrical characteristics
DDA
DDA
= 3.0 V – 3.6 V
> 3.6 V – 5.5 V
Characteristic
1
Table 20. ADC conversion specifications (operating)
Table 21. Flash program and erase specifications
Characteristic
PXN20 Microcontroller Data Sheet, Rev. 1
4
PLL
4
value greater than the f
SYS
Symbol
F
GNE
AV
DNL
OFS
TUE
.
V
V
INL
F
MAX
t
RH
RL
S
S
IN
PLL
maximum specified value.
V
DDA
–1.0
–1.5
–1.0
–2.0
–2.0
Min
V
250
125
—
—
t
0
RL
t
t
128kpperase
t
16kpperase
64kpperase
– 0.5
Symbol
dwprogram
t
pprogram
1
Min
—
—
—
—
—
Electrical characteristics
V
Max
1.53
V
0.5
1.0
1.5
1.0
2.0
2.0
60
DDA
—
Initial
RH
Max
1000
1800
2600
160
jitter
—
2
+ C
DDE
Max
5000
5000
7500
mod
500
500
segment.
.
3
MHz
MHz
Unit
LSB
LSB
LSB
LSB
LSB
ns
V
V
V
Unit
ms
ms
ms
s
s
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