MPXN2120VMG116 Freescale Semiconductor, MPXN2120VMG116 Datasheet - Page 54

• Manufacturer Part Number: MPXN2120VMG116
• Description: Microprocessors - MPU 32BIT2M NVM GATEWAY
• Manufacturer: Freescale Semiconductor

Specifications of MPXN2120VMG116

• Rohs: yes
• Processor Series: PXN21
• Core: e200
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 60 MHz
• Program Memory Size: 2 MB
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SPI, UART
• Operating Supply Voltage: - 0.3 V to + 1.32 V
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-208
• Number Of Programmable I/os: 155

Electrical characteristics
1
2
3
54
• Ground = 0.0V
• Load Capacitance = 60 pF, SIU_PCR144–SIU_PCR146[DSC] = 0b11.
• MLB speed of 256 Fs or 512 Fs (Fs = 48 kHz)
• Ground = 0.0V
• Load Capacitance = 40 pF, SIU_PCR144–SIU_PCR146[DSC] = 0b00.
• MLB speed = 1024Fs (Fs = 48 kHz)
• Unless otherwise noted, timing parameters are specified from the valid voltage threshold in
The Controller can shut off MLBCLK to place MLB in a low-power state.
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (ns p-p).
The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
Spec
Unless otherwise noted, all timing parameters are specified from the valid voltage threshold in
Spec
10
11
12
10
11
12
1
2
3
4
5
6
7
8
9
MLBSIG/MLBDAT output high
impedance from MLBCLK low
Bus Hold time
MLBSIG/MLBDAT output valid from
MLBCLK rising
MLBCLK Operating Frequency
MLBCLK rise time
MLBCLK fall time
MLBCLK cycle time
MLBCLK low time
MLBCLK high time
MLBCLK pulse width variation
MLBSIG/MLBDAT input valid to
MLBCLK falling
MLBSIG/MLBDAT input hold from
MLBCLK low
MLBSIG/MLBDAT output high
impedance from MLBCLK low
Bus Hold time
MLBSIG/MLBDAT output valid from
MLBCLK rising
Table 31. MLB timing for MLB speed 256 Fs or 512 Fs (continued)
Parameter
Parameter
3
3
Table 32. MLB timing for MLB speed 1024 Fs
PXN20 Microcontroller Data Sheet, Rev. 1
2
1
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
mcfdz
mcrdv
t
t
dsmcf
dhmcf
mcfdz
mcrdv
f
mpwv
mdzh
mckh
mdzh
mckc
mckr
mckf
mckl
mck
45.056
Min
Min
6.5
6.1
9.7
9.3
—
—
—
—
—
—
—
—
—
0
4
1
0
0
2
49.152
20.3
10.6
10.2
Typ
Typ
7.7
7.3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
49.2544
51.200
Max
Max
t
t
mckl
0.7
mckl
—
—
—
—
—
—
—
—
—
8
1
1
7
ns p-p
Table
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table
30.
Freescale Semiconductor
1024 Fs at 44.0 kHz
1024 Fs at 48.0 kHz
1024 Fs at 48.1 kHz
1024 Fs PLL unlocked
V
V
V
1024 Fs
PLL unlocked
1024 Fs
PLL unclocked
IL
IH
IL
30.
to V
to V
to V
Comments
Comments
IH
IH
IL
—
—
—