MPXN2120VMG116 Freescale Semiconductor, MPXN2120VMG116 Datasheet - Page 55

• Manufacturer Part Number: MPXN2120VMG116
• Description: Microprocessors - MPU 32BIT2M NVM GATEWAY
• Manufacturer: Freescale Semiconductor

Specifications of MPXN2120VMG116

• Rohs: yes
• Processor Series: PXN21
• Core: e200
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 60 MHz
• Program Memory Size: 2 MB
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SPI, UART
• Operating Supply Voltage: - 0.3 V to + 1.32 V
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-208
• Number Of Programmable I/os: 155

1
2
3
4.14.7
MII signals use CMOS signal levels compatible with devices operating at either 5.0 V or 3.3 V. Signals are not TTL compatible.
They follow the CMOS electrical characteristics.
4.14.7.1
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency.
Freescale Semiconductor
The Controller can shut off MLBCLK to place MLB in a low-power state.
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (ns p-p).
The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
Spec
M1
M2
M3
M4
RXD[3:0], RX_DV, RX_ER to RX_CLK setup
RX_CLK to RXD[3:0], RX_DV, RX_ER hold
RX_CLK pulse width high
RX_CLK pulse width low
MLBSIG/
MLBDAT
MLBCLK
MLBSIG/
MLBDAT
Fast Ethernet Controller (FEC) interface
(output)
MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
(input)
2
Characteristic
Figure 23. Media Local Bus (MLB) timing
PXN20 Microcontroller Data Sheet, Rev. 1
Table 33. MII receive signal timing
12
4
6
valid data
valid data
10
8
35%
35%
Min
5
5
3
9
5
11
Max
65%
65%
—
—
Electrical characteristics
RX_CLK period
RX_CLK period
Unit
ns
ns
55