PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet
PCI-MT32-XP-N1
Specifications of PCI-MT32-XP-N1
Related parts for PCI-MT32-XP-N1
PCI-MT32-XP-N1 Summary of contents
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... PCI IP User’s Guide November 2010 IPUG18_09.2 ...
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... Local Bus Interface ............................................................................................................................................. 30 Target Operation ........................................................................................................................................ 30 Master Operation ....................................................................................................................................... 30 Basic PCI Master Read and Write Transactions................................................................................................. 31 32-bit PCI Master with a 32-bit Local Bus .................................................................................................. 31 64-Bit PCI Master with a 64-Bit Local Bus ................................................................................................. 35 32-bit PCI Master with a 64-Bit Local Bus.................................................................................................. 40 Configuration Read and Write Transactions .............................................................................................. 46 PCI Master I/O Read and Write Transactions............................................................................................ 46 Advanced Master Transactions ...
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... Lattice Semiconductor 32-bit PCI Target with a 32-bit Local Bus Memory Transactions ............................................................... 82 64-Bit PCI Target with a 64-Bit Local Bus.................................................................................................. 87 32-Bit PCI Target with a 64-Bit Local Bus.................................................................................................. 90 Configuration Read and Write Transactions .............................................................................................. 94 PCI Target I/O Read and Write Transactions ............................................................................................ 96 Advanced Target Transactions ........................................................................................................................... 97 Wait States................................................................................................................................................. 97 Burst Read and Write Target Transactions ...
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... PCI Pin Assignments for Master/Target 33MHz 32-Bit Bus..................................................................... 168 PCI Pin Assignments for Target 33MHz 32-Bit Bus................................................................................. 169 PCI Pin Assignments for Master/Target 33MHz 64-Bit Bus..................................................................... 171 Pin Assignment Considerations for MachXO Devices ...................................................................................... 173 PCI Pin Assignments for Target 33MHz 32-Bit Bus................................................................................. 173 PCI Pin Assignments for Target 66MHz 32-Bit Bus ...
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... PCI Pin Assignments for Target 33 MHz 64-bit Bus ................................................................................ 183 PCI Pin Assignments for Master/Target 66 MHz 32-bit Bus .................................................................... 185 PCI Pin Assignments for Master/Target 66 MHz 64-bit Bus .................................................................... 187 PCI Pin Assignments for Target 66 MHz 32-bit Bus ................................................................................ 189 PCI Pin Assignments for Target 66 MHz 64-bit Bus ................................................................................ 191 IPUG18_09 ...
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... PCI Master and Target or Target only solution that is fully compliant with the PCI Local Bus Specification, Revision 3.0 for speeds up to 66MHz. The PCI cores bridge the gap between the PCI Bus and specific design applications, providing an integrated PCI solution. These cores allow designers to focus on the application rather than on the PCI specification, resulting in a faster time-to-market ...
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... Lattice Semiconductor Table 1-2. PCI IP Core Quick Facts--PCI master/target 66MHz/32bit FPGA Families Supported Core Requirements Minimal Device Needed Data Path Width Resource Utilization LUTs Registers Lattice Implementation Design Tool Synthesis Support Simulation Table 1-3. PCI IP Core Quick Facts--PCI master/target 33MHz/64bit FPGA Families Core ...
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... Lattice Semiconductor Table 1-4. PCI IP Core Quick Facts--PCI master/target 33MHz/32bit FPGA Families MachXO Supported Core Requirements Minimal LCMXO1200 Device E-5FT256C Needed Data Path Width Resource LUTs Utilization Registers Lattice Implemen- tation Design Tool Synthesis Support Simulation Table 1-5. PCI IP Core Quick Facts--PCI target 66MHz/64bit ...
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... Lattice Semiconductor Table 1-6. PCI IP Core Quick Facts--PCI target 66MHz/32bit FPGA Families Core Supported Requirements Minimal Device Needed Data Path Width Resource LUTs Utilization Registers Lattice Implementation Design Tool Synthesis Support Simulation Table 1-7. PCI IP Core Quick Facts--PCI target 33MHz/64bit ...
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... Tool Sup- Synthesis port Simulation Features • Available as 32/64-bit PCI bus and 32/64-bit local bus • PCI SIG Local Bus Specification, Revision 3.0 compliant • 64-bit addressing support (dual address cycle) • Capabilities list pointer support • Parity error detection • six Base Address Registers (BARs) • ...
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... The PCI Master Control interfaces with the PCI bus. It supports all of the address and command signals required to execute transactions on the PCI bus for both 32-bit and 64-bit PCI applications. A list of the supported PCI signals is available in the PCI Interface Signals section of this document. Once the Local Master Interface Control is granted the bus, it passes the transaction information to the PCI Master Control using the internal bus ...
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... The PCI Target control interfaces with the PCI bus. It processes the address, data, command and control signals to transfer data to and from the PCI IP core for both 32-bit and 64-bit PCI applications. A list of the supported PCI sig- nals is available in the PCI Interface Signals section. Once the PCI Target control detects a transaction, it passes the transaction information to the Local Interface control using the internal bus ...
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... The Configuration Space implements all the necessary Configuration Space registers required to support a single- function PCI IP core. It provides the first 64 bytes of header type 0, which is used for all device types other than PCI-to-PCI and CardBus bridges. The first 64 bytes of the predefined header region contain fields that uniquely identify the device and allow the device to be generically controlled ...
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... PCI IP core. These are the signals required by the PCI IP core to handle PCI bus side transactions. describes each signal. In addition to the signals required by the PCI IP core, there are some signals on the PCI Bus, referred to as “Addi- tional Signals” in the PCI specifications, which must be handled appropriately to insure proper PCI IP core func- tions in a system ...
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... Local Interface Signals The Local Interface provides all the necessary address and control signals to respond to and initiate transactions associated with the PCI bus. Command and status information are also available at the Local Interface, so the back-end application logic can essentially monitor the PCI bus. ...
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... Local master byte enables. The local side interrupt request indicates that the Local Interface is request- low ing an interrupt. This signal asserts the PCI side interrupt signal, intan, if interrupts are enabled in the Configuration Space. The cache signal indicates the cache length in the cache registers defined — ...
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... IPUG18_09.2, November 2010 1 (Continued) Polarity low Local target abort request is used to request a target abort on the PCI bus. Local target disconnect (or retry) is used to request early termination of a low bus transaction on the PCI bus. Local target ready signal indicates that the Local Interface is ready to low receive or send data ...
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... During Master Read operation the signal lm_data_xfern always reflects valid data in the local data bus. But during Master Write opera- tion, due to data prefetch ahead of the transactions on PCI bus, lm_data_xfern along with the lm_status reflects the data validity. If lm_status is 0100, (meaning a Bus Termination) ignore the lm_data_xfern assertion because the data being prefetched is not sent out on the PCI bus due to termination ...
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... Vendor ID: The Vendor 16-bit, read-only field used to identify the manufacturer of the product. The Vendor ID is set using the VENDOR_ID parameter. The Vendor ID is assigned by the PCI SIG to ensure uniqueness. Con- tact PCI SIG (www.pcisig.org) to obtain a unique Vendor ID. ...
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... Memory Space Enable controls a device’s response to memory space accesses. Memory space accesses are 1 enabled if the bit is set After reset the memory space enable bit is set Bus Master enables the PCI IP core to act as a master on the PCI bus when this bit is set to 1. After reset the Bus 2 Master enable bit is set ...
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... The Status Register is a 16-bit read/write register that provides information on the capabilities of the PCI IP core. It also reports the error status of the PCI IP core. The Status Register is located at the upper 16 bits of register loca- tion 04h. Writes to the Status Register from the PCI bus are slightly different, given that bits can be reset but not set ...
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... The PCI IP core supports up to six Base Address Registers (BARs) for Master/Target and Target configurations. The BAR holds the base address for the PCI IP core, and it is used to point to the starting address of the PCI IP core in the system memory map. They are configured differently based on whether they are mapped in memory or I/O space ...
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... Latency Timer The Latency Timer register is an eight-bit read/write or read only register, located at byte address 0Dh. It specifies the Master Latency Timer value for a PCI Master on the PCI bus. During reset the register is set to 00h. CardBus CIS Pointer The CardBus CIS Pointer is a read-only, 32-bit register at location 28h in the Configuration Space. The CIS_POINTER parameter determines the value of the register ...
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... Master to control the PCI bus. It resides in the upper 8 bits of address location 3Ch. The MIN_GRANT parameter determines the value of this register. Max_Lat The Max_Lat read-only register is an 8-bit field that is used to specify the how often the PCI IP core the bus. It resides in the third byte of address location 3Ch. The MAX_LATENCY parameter determines the value of this regis- ter. ...
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... The value for PCI Data Bus size is set in each eval configuration as described in the appendices of the PCI IP core data sheet. 2. For 32-bit PCI Data Bus, only 32-bit Local Data Bus sizes are supported. For 64-bit PCI Data Bus, only 64-bit Local Data Bus sizes ...
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... The GUI provides a range checking routine that ensures the selected values are within the core’s valid range. If the user configures this PCI IP core outside of the GUI flow the user’s responsibility to ensure that the parameter values are within the valid ranges shown in range will cause the PCI IP core to function improperly. The recommended flow is to follow example 2 above and use the PCI GUI to generate the params.v file. The name of this generated output file is fixed at “ ...
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... Medium (not supported Slow 11 - Reserved Enable for the Capabilities Pointer used to set the enable bit for the Capabilities List in the PCI Status register. This bit is used to Enabled/Disabled Enabled indicate if the value of the Capabilities Pointer at location 34h is valid. This is bit 4 in the sta- tus register ...
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... BAR5_g IPUG18_09.2, November 2010 Range Default PCI value for the Status field bit to enable 66MHz. This is bit 5 in the status register indicates that the PCI IP core is 66MHZ capable, and a 0 indicates that it is not. The default value is 1. ...
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... In this case: • Content of that BAR register in PCI Configuration Space is 0x0000_0000 The default values shown are the read back value (using PCI read command) of the enabled BAR after all 1’s are written into that BAR (using PCI write command). Bar Configuration Details ...
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... Local Bus Interface Target Operation Initially, the local target is idle. A valid transaction in the PCI bus is indicated to the local bus side by the assertion of lt_accessn signal. At this time either the bar_hit, new_cap_hit or exprom_hit signal indicates whether a BAR or New Capabilities register is selected, and lt_command_out indicates the current PCI command. If the command is Special Cycle, then no BAR is selected, otherwise the selected BAR needs to prepare the next pro- cess ...
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... Driven bus signals or driven PCI parity signal (par and par64). Data 4 Floated PCI signals. If the signal is high high maintained by system pull-up resistor. If the signal is in the middle of level place tri-state. Don’t care local signal. For input signal, the core doesn’t read it. For output signal invalid value. ...
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... Don’t care 32 Functional Description Data 1 Byte Enable 1 Address Data Parity Parity 1 Don’t care Byte Enable 1 Don’t care Don’t care Bus Bus Transaction Termination Data 1 Don’t care Bus Length Normal Termination PCI IP Core User’s Guide 11 ...
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... Idle request the use of PCI bus. 3 Idle gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master. Since gntn is asserted and the current bus is idle, the Core starts the bus transactions. The 4 Idle Core asserts lm_gntn to inform the local master that the bus request is granted. ...
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... Loading Don’t care Don’t care 34 Functional Description Data 1 Byte Enable 1 Address Data Parity 1 Parity Don’t care Don’t care Don’t care Bus Bus Transaction Termination Bus Length Normal Termination PCI IP Core User’s Guide ...
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... PCI Master with a 64-Bit Local Bus This section discusses read and write transactions for a PCI IP core configured with a 64-bit PCI bus and a 64-bit local bus. The PCI Specification requires all 64-bit PCI master devices to execute both 64-bit and 32-bit transac- tions ...
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... Parity Data Parity 2 Don’t care Byte Enable 1 Don’t care Byte Enable 2 Don’t care Don’t care Bus Bus Transaction Termination Data 1 Don’t care Data 2 Don’t care Bus Length Normal Termination PCI IP Core User’s Guide ...
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... Idle the use of PCI bus. 3 Idle gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master. Since gntn is asserted and the current bus is idle, the Core is going to start the bus transactions. 4 Idle The master asserts lm_gntn to inform the local master that the bus request is granted. ...
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... Lattice Semiconductor The 64-bit memory write transaction is similar to the 32-bit target write transaction with additional PCI signals required for 64-bit signaling. Figure 2-10 Figure 2-10. 64-bit Master Single Write Transaction with a 64-bit Local Interface 1 2 clk reqn gntn framen req64n ad[31:0] ad[63:32] cben[3:0] cben[7:4] par ...
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... Idle the use of PCI bus. 3 Idle gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master. Since gntn is asserted and the current bus is idle, the Core is going to start the bus transactions. 4 Idle The Core asserts lm_gntn to inform the local master that the bus request is granted. ...
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... This section discusses read and write transactions executed by the PCI IP core configured with a 32-bit PCI bus and a 64-bit local bus. The 32-bit PCI master transactions, described in the 32-Bit PCI Master and 32-Bit Local Bus section, are similar to these master transactions; however; the data is handled differently at the Local Master Inter- face ...
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... Byte Enable 1 Don’t care Data Data Parity 1 Parity 2 Don’t care Don’t care Don’t care Don’t care Bus Bus Transaction Termination Data 1 Don’t care Data 2 Don’t care Normal Termination PCI IP Core User’s Guide ...
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... Idle the use of PCI bus. 3 Idle gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master. Since gntn is asserted and the current bus is idle, the Core is going to start the bus transactions. 4 Idle The Core asserts lm_gntn to inform the local master that the bus request is granted. ...
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... The Core relinquishes control of irdyn and de-asserts lm_hdata_xfern, and the local master 12 Idle de-asserts lm_rdyn since all of the burst data have been read. The 64-bit memory write transaction is similar to the 32-bit write transaction with additional PCI signals required for 64-bit signaling. Figure 2-12 and IPUG18_09 ...
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... Byte Byte Enable 1 Enable 2 Don’t care Data Data Parity 1 Parity 2 Don’t care Don’t care Don’t care Don’t care Don’t care Don’t care Bus Bus Transaction Termination Normal Termination PCI IP Core User’s Guide ...
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... Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle. Since the previous data phase was completed, the Core decreases lm_burst_cnt. Since Data 1 PCI bus was read by the target, the Core transfers Data 2 and the byte enables to ad[31:0] and cben[3:0]. ...
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... Care must be taken when processing wait states to be compliant with the PCI Local Bus Specification, Revision 3.0. Once a PCI master or a PCI target signals that it is ready to send or receive data, it must complete the current PCI data phase. For example, if the PCI IP core target, is ready to write data and the PCI master inserts wait states, the PCI IP core must wait to write the data until the master is ready again ...
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... The master detects the asserted lm_req32n and asserts reqn to request the use of PCI bus. 3 Idle gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master. Since gntn is asserted and the current bus is idle, the Core starts the bus transactions. The Core 4 Idle asserts lm_gntn to inform the local master that the bus request is granted ...
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... Because this is not the last cycle transaction, the Core keeps framen. The target asserts devseln to response the command. The Core de-asserts lm_gntn to follow gntn. With the trdyn asserted, Data 1 is driven on to ad[31:0]. If the PCI IP core is ready to receive 8 Data 1 data, irdyn remains asserted and it keeps the Byte Enables on cben[3:0]. ...
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... Table 2-18 show master-inserted and target-inserted wait states occurring on write transactions. The figure illustrates the correlation of the PCI interface to the Local Master Interface. The table gives a clock-by- clock description of each event in the figure. Figure 2-14. 32-bit Master Write Transaction with Local Wait State ...
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... And the Core asserts lm_data_xfern to the local master to signify these data and byte enables are being read and will be transferred to the PCI bus. Data 2 will be buffered and put on PCI bus after Data 1 phase fin- ished. ...
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... PCI Master with a 64-Bit Local Bus • 32-Bit PCI Master with a 64-Bit Local Bus 32-Bit PCI Master and a 32-bit Local Bus The following section discusses read and write burst data transfers for a PCI IP core configured with a 32-bit PCI bus and a 32-bit Local bus. Figure 2-15 The figure illustrates how the PCI interface correlates to the Local Master Interface ...
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... Idle the use of PCI bus. 3 Idle gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master. Since gntn is asserted and the current bus is idle, the Core starts the bus transactions. The mas- 4 Idle ter asserts lm_gntn to inform the local master that the bus request is granted. ...
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... Loading’ and if it doesn’t want to request another PCI bus transaction. lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives the PCI starting address on ad[31:0] and the PCI command on cben[3:0]. On the same cycle, it outputs lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the address/data phases. 6 Address lm_burst_cnt gets the value of the burst length ...
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... The figure illustrates how the PCI interface correlates to the Local Master Interface. The table gives a clock-by-clock description of each event that occurs in the figure. ...
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... Idle the use of PCI bus. 3 Idle gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master. Since gntn is asserted and the current bus is idle, the Core is going to start the bus transactions. 4 Idle The Core asserts lm_gntn to inform the local master that the bus request is granted. ...
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... Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle. Since the previous data phase was completed, the Core decreases lm_burst_cnt. Since Data 1 on PCI bus were read by the target, the Core transfers Data 2 and their byte enables to ad[31:0] and cben[3:0]. ...
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... Lattice Semiconductor 64-bit PCI Master with a 64-bit Local Bus The following discusses read and write burst transactions for the PCI IP core configured with a 64-bit PCI bus and a 64-bit Local bus. Figure 2-17 and PCI Interface correlates to the Local Master Interface. The table gives a clock-by-clock description of each event that occurs in the figure ...
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... Data Data Parity 2 Parity 4 Parity 6 Don’t care Don’t care Don’t care Don’t care Bus Bus Transaction Termination Data 1 Data 3 Data 5 Don’t care Data 2 Data 4 Data 6 Don’t care Normal Termination PCI IP Core User’s Guide ...
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... Idle the use of PCI bus. 3 Idle gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master. Since gntn is asserted and the current bus is idle, the Core is going to start the bus transactions. 4 Idle The Core asserts lm_gntn to inform the local master that the bus request is granted. ...
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... Data 5 and 6. The Core relinquishes control of irdyn and de-asserts lm_ldata_xfern and 12 Idle lm_hdata_xfern, and the local master de-asserts lm_rdyn since all of the burst data have been read. IPUG18_09.2, November 2010 Functional Description Description 60 PCI IP Core User’s Guide ...
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... Figure 2-18 and Table 2-22 illustrate a 64-bit burst write transaction. The figure shows how the PCI interface corre- lates to the Local Master Interface. The table gives a clock-by-clock description of each event that occurs in the fig- ure. Figure 2-18. 64-bit Master Burst Write Transaction with a 64-bit Local Interface ...
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... Idle the use of PCI bus. 3 Idle gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master. Since gntn is asserted and the current bus is idle, the Core is going to start the bus transactions. 4 Idle The Core asserts lm_gntn to inform the local master that the bus request is granted. ...
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... PCI Master with a 64-Bit Local Bus The following discusses read and write transactions for a PCI IP core configured with a 32-bit PCI bus and a 64-bit local bus. Two PCI data phases are required when writing or reading 64-bit data via the Local Master Interface. ...
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... Table 2-23 illustrate a burst transaction to a 32-bit PCI IP core with a 64-bit Local Master Interface. The figure illustrates how the PCI interface correlates to the Local Master Interface. The table gives a clock-by- clock description of each event in the figure. IPUG18_09.2, November 2010 Functional Description 64 PCI IP Core User’ ...
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... Byte Enable 1 Don’t care Byte Enable 2 Don’t care Don’t care Bus Bus Transaction Termination Data 1 Don’t care Data 3 Don’t care Data 2 Don’t care Data 4 Don’t care Normal Termination PCI IP Core User’s Guide 14 ...
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... Idle the use of PCI bus. 3 Idle gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master. Since gntn is asserted and the current bus is idle, the Core starts the bus transactions. The Core 4 Idle asserts lm_gntn to inform the local master that the bus request is granted. ...
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... With lm_hdata_xfern asserted, the local master can safely read Data 4. The Core relinquishes control of irdyn and de-asserts lm_ldata_xfern and 12 Idle lm_hdata_xfern, and the local master de-asserts lm_rdyn since all of the burst data have been read. IPUG18_09.2, November 2010 Functional Description Description 67 PCI IP Core User’s Guide ...
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... Table 2-24 illustrate a burst transaction for a 32-bit PCI IP core with a 64-bit Local Interface. The figure shows how the PCI interface correlates to the Local Interface. The table gives a clock-by-clock description of each event illustrated in the figure. Figure 2-20. 32-bit Master Burst Write Transaction With a 64-bit Local Interface ...
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... Idle the use of PCI bus. 3 Idle gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master. Since gntn is asserted and the current bus is idle, the Core starts the bus transactions. The Core 4 Idle asserts lm_gntn to inform the local master that the bus request is granted. ...
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... The Core relinquishes control of irdyn, par and par64. Dual Address Cycle (DAC) The PCI IP core application logic issues a Dual Address Cycle (DAC) command to inform the PCI IP core of its usage of 64-bit addressing. In response, the Core executes two back-to-back address phases for the target. The PCI IP core issues DAC to handle memory maps that are larger than the 4GB limitation of the 32-bit memory map ...
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... Idle the use of PCI bus. 3 Idle gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master. Since gntn is asserted and the bus is idle, the Core starts the bus transactions. The Core asserts 4 Idle lm_gntn to inform the local master that the bus request is granted. ...
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... Since lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives the PCI start- Low 6 ing address on ad[31:0] and the PCI command (DAC) on cben[3:0]. On the same cycle, it Address keeps lm_status[3:0] as ‘Address Loading’ for the Dual Address Cycle. Local master provides higher address on l_ad_in[31:0]. ...
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... The Core relinquishes control of irdyn and de-asserts lm_data_xfern, and the local master 12 Idle de-asserts lm_rdyn since all of the burst data have been read. Figure 2-22 shows an example of the DAC during a 32-bit write transaction. description of the dual address cycle. IPUG18_09.2, November 2010 Functional Description Description Table 2-26 73 PCI IP Core User’s Guide gives a clock-by-clock ...
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... Idle the use of PCI bus. 3 Idle gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master Since gntn is asserted and the current bus is idle, the Core is going to start the bus transactions. 4 Idle The Core asserts lm_gntn to inform the local master that the bus request is granted. ...
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... Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle. Since the previous data phase was completed, the Core decreases lm_burst_cnt. Since Data 1 on PCI bus were read by the target, the Core transfers Data 2 and their byte enables to ad[31:0] and cben[3:0]. ...
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... The Core relinquishes control of irdyn and par. Fast Back-to-Back Transactions The PCI IP core master, is capable of executing fast back-to-back transactions if two or more consecutive transactions are required. The fast back-to-back transaction consists of two or more complete PCI transactions without an idle state between them. To execute fast back-to-back transaction with the PCI IP core, lm_req32n or lm_req64n must be asserted once lm_status changes to the ‘ ...
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... Data 6 Data 8 Don’t care Byte Byte Enable 7 Don’t care Enable 5 Byte Byte Enable 8 Don’t care Enable 6 Don’t care Bus Bus Transaction Termination Bus Length Normal Normal Don’t care Termination Termination PCI IP Core User’s Guide 19 ...
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... Data 1 and Data 2 on l_ad_in[63:0] and the byte enables on lm_cben_in[7:0]. And the Core asserts lm_ldata_xfern and lm_hdata_xfern to the local master to signify these data and byte enables are being read and will be transferred to the PCI bus. Asserting lm_rdyn means the local master is ready to write data not, it keeps lm_rdyn de- asserted until it is ready ...
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... Since Data 1 and Data 2 on PCI bus were read by the target, the Core transfers Data 3 and Data 4 and their byte enables to ad[63:0] and cben[7:0]. The Core de-asserts framen and req64n, asserts irdyn to signal Data 3 and 4 transferred. ...
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... Since both irdyn and trdyn are asserted, the first data phase is completed on this cycle. Since the previous data phase was completed, the Core decreases ‘lm_burst_cnt’. Since Data 5 and Data 6 on PCI bus were read, the Core transfers Data 7 and Data 8 and their byte enables to ad[63:0] and [7:0]. ...
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... Grant abort termination 111 Local master termination Basic PCI Target Read and Write Transactions Read and write transactions to memory and I/O space are used to transfer data on the PCI bus. The basic read and write transactions use the following PCI commands: • I/O Read • I/O Write • ...
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... PCI Target with a 32-bit Local Bus Memory Transactions This section discusses read and write transactions for the PCI IP core, operating as a Target, configured with a 32- bit PCI bus and a 32-bit local bus. Because 32-bit I/O and memory transactions are alike, they are discussed together ...
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... IPUG18_09.2, November 2010 Don’t care Byte Enable 1 Address Parity Don’t care 83 Functional Description Data 1 Data Don’t care Parity 1 0x01 Data 1 Don’t care Byte Enable 1 Don’t care Address Bus Command PCI IP Core User’s Guide 9 0x00 ...
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... Turn around The PCI IP core starts to decode the address and command It also registers and drives the lt_address_out lt_command_out to the back end. If there is an address match, the Core drives the bar_hit signals to the back-end. It also asserts 3 Wait lt_accessn ...
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... Lattice Semiconductor Figure 2-25 illustrates an example of a basic 32-bit write transaction to the PCI IP core operating as a Target. Table 2-30 gives a clock-by-clock description of the 32-bit write transaction. Figure 2-25. 32-bit Target Single Write Transaction with a 32-bit Local Interface 1 clk framen ad[31:0] Address Bus cben[3:0] Command ...
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... The master also de-asserts irdyn since only one data 6 Turn around phase is required. The Core asserts lt_data_xfern to indicate that the valid PCI data is avail- able for writing. The Core relinquishes control of devseln and trdyn.The target clears bar_hit to signal to the ...
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... This section discusses read and write transactions for a PCI IP core, operating as a target, configured with a 64-bit PCI bus and a 64-bit local bus. All 64-bit PCI devices are required by the PCI Specification to handle both 64-bit and 32-bit applications. The 32-bit transactions, described in the 32-Bit PCI Target with a 32-Bit Local Bus Memory Transactions section, are similar to a 32-bit transaction for the 64-bit PCI IP core configuration with the exception that when the 64-bit Core responds to a 32-bit transaction the upper 32 bits of the data bus should be ignored ...
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... Turn around trdyn and irdyn were asserted during the last cycle. The Core also clears bar_hit to signal to the back-end that the transaction is complete. The Core de-asserts lt_hdata_xfern and lt_ldata_xfern. 10 Idle IPUG18_09.2, November 2010 Functional Description Description 88 PCI IP Core User’s Guide ...
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... Lattice Semiconductor The 64-bit memory write transaction is similar to the 32-bit target write transaction with additional PCI signals required for 64-bit signaling. Figure 2-27 Figure 2-27. 64-bit Target Single Write Transaction with a 64-bit Local Interface framen req64n ad[31:0] ad[63:32] cben[3:0] cben[7:4] devseln ack64n bar_hit[5:0] lt_accessn lt_r_nw ...
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... Bus Memory Transactions section, look similar to the transaction; however; the data is handled differently at the Local Target Interface. In order to present a full 64 bits of data to the Local Target Interface, two PCI data phase are required. Like retriev- ing 64 bits of data from the Local Target Interface, two PCI data phases are required The Local Target Interface control latches the complete QWORD and routes the proper DWORD to the PCI data bus ...
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... Don't care Data 1 Don't care Byte Enable 1 Byte Enable 1 Bus Command 91 Functional Description Data 1 Data 2 Data Data Parity 1 Parity 2 0x01 Don't care Data 3 Don't care Data 2 Don't care Address PCI IP Core User’s Guide 10 0x00 Don't care Don't care ...
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... The Core relinquishes control of devseln and trdyn.The Core also signals to the back-end that 9 Idle the transaction is complete by clearing bar_hit. The Core de-asserts lt_data_xfern. The 64-bit memory write transaction is very similar to the 32-bit target write transaction with additional PCI signals required for 64-bit signaling. Figure 2-29 IPUG18_09.2, November 2010 ...
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... Byte Enable 1 Don’t care Bus Command 93 Functional Description Data 2 Byte Enable 2 Data Parity 2 0x01 0x00 Data 1 Don’t care Data 2 Don’t care Don’t care Don’t care Byte Don’t care Enable 2 Address PCI IP Core User’s Guide 9 ...
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... However, these transactions are still pro- vided for verification purposes. The PCI IP core only supports 32-bit, single data phase transactions to configuration registers. An individual idsel signal is connected to each PCI IP core device. Otherwise, read and write transactions are like the standard mem- ory and I/O transactions. Figure 2-30 Table 2-36 shows an example of a configuration write ...
Page 95
... Idle The Core relinquishes control of devseln, trdyn and stopn. IPUG18_09.2, November 2010 Don’t care Data 1 Byte Enable 1 Address Don’t care Parity Description 95 Functional Description Data Parity 1 PCI IP Core User’s Guide ...
Page 96
... Designing a PCI target application using I/O space is not recommended for several reasons. They include legacy device conflicts, and full address and byte enable decoding for all I/O locations. However, the PCI IP core does sup- port I/O space. Transactions to I/O locations are similar to the basic memory transactions discussed in the Basic PCI Target Read and Write Transactions section ...
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... Care must be taken when processing wait states to be compliant with the PCI Local Bus Specification, Revision 3.0. Once a PCI master or a PCI target signals that it is ready to send or receive data, it must complete the current PCI data phase. For example, if the PCI IP core is ready to write data and the PCI master inserts wait states, the PCI IP core must wait to write the data until the master is ready again ...
Page 98
... Target Wait The back-end logic asserts lt_rdyn during this cycle. The PCI IP core inserts a wait state as it has not yet asserted the trdyn signal. Since both irdyn 5 Target Wait and lt_rdyn were asserted on the previous cycle, the Core asserts lt_data_xfern. ...
Page 99
... Table 2-38 show master-inserted and target-inserted wait states that are inserted on write transac- tions. The figure illustrates how the PCI interface correlates to the Local Target Interface. The table gives a clock- by-clock description of each event in the figure. Figure 2-33. 32-bit Target Write Transaction with Master Wait State ...
Page 100
... Typically for burst transactions, the PCI master and the PCI target has a predefined number of PCI data phases that are to be transferred. The PCI master will know the number of data phases that are to be transferred based on the software driver and specifications that were defined by the PCI IP core’s implementation. The PCI IP core will have a predefined number of data phases based on the design requirements of the PCI Target core’ ...
Page 101
... Lattice Semiconductor 32-Bit PCI Bus and a 32-Bit Local Bus The following section discusses read and write, burst transactions for a PCI IP core configured with a 32-bit PCI bus and a 32-bit Local bus. Figure 2-34 how the PCI interface correlates to the Local Target Interface. The table gives a clock-by-clock description of each event that occurs in the figure ...
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... The back-end can increment the address counter and put the next DWORD (Data 3) on l_ad_in. If the PCI master is still ready to receive data, it keeps irdyn asserted and drives the next byte enables (Byte Enable 3) on cben[3:0]. The master signals the end of the burst when it de-asserts framen.If the back-end keeps ...
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... The assumption is that the device select timing is set to slow and wait states are not inserted. The figure illustrates how the PCI interface correlates to the Local Target Interface. The table gives a clock-by-clock description of each event that occurs in the figure. ...
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... Wait to write data, it asserts irdyn and drives the first DWORD (Data 1) on ad[31:0]. The PCI IP core starts to decode the address and command and drives the lt_address_out to the back-end. If there is an address match, the Core drives the bar_hit signals on the Local Interface. The back- ...
Page 105
... PCI interface correlates to the local interface. The table gives a clock-by-clock description of each event that occurs in the figure. The 32-bit burst transaction, as described in the 32-Bit PCI Bus and a 32-Bit Local Bus section, is similar to a 32-bit burst transaction for the 64-bit PCI IP core configuration. When the 64-bit target core responds to a 32-bit burst transaction, the upper 32 bits of the data bus should be ignored ...
Page 106
... Byte Enable 2 Address Bus Command 106 Functional Description Data 3 Data 5 Data 4 Data 6 Data Data Data Parity 1 Parity 3 Parity 5 Data Data Data Parity 2 Parity 4 Parity 6 0x00 Data 5 Don't care Data 6 Don't care Don't care Don't care PCI IP Core User’s Guide ...
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... The back-end application can increment the address counter and put the next QWORD (Data 5 and 6) on l_ad_in. If the PCI master is still ready to receive data, it keeps irdyn asserted and drives the next byte enables (Byte Enable 5 and 6) on cben[7:0]. ...
Page 108
... Table 2-42 illustrate a 64-bit burst write transaction. The figure shows how the PCI interface corre- lates to the Local Interface. The table gives a clock-by-clock description of each event that occurs in the figure. Figure 2-37. 64-bit Target Burst Write Transaction with a 64-bit Local Interface ...
Page 109
... The following discusses read and write transactions for a PCI IP core configured with a 32-bit PCI bus and a 64-bit local bus. In order to present a full 64 bits of data to the Local Interface, two PCI data phase are required. Likewise retrieving 64 bits of data from the Local Interface, two PCI data phases are required. ...
Page 110
... Table 2-43 illustrate a burst transaction to a 32-bit PCI IP core with a 64-bit Local Interface. The figure illustrates how the PCI interface correlates to the Local Interface. The table gives a clock-by-clock description of each event in the figure. Figure 2-38. 32-bit Target Burst Read Transaction with a 64-bit Local Interface ...
Page 111
... QWORD aligned. The back-end drives the first QWORD (Data 1 and Data 2) on l_ad_in. Quad Word Aligned With lt_rdyn asserted for the previous two cycles, the burst cycle starts. The PCI IP core asserts trdyn and puts Data 1 on ad[31:0]. The Core de-asserts lt_ldata_xfern. If irdyn is asserted on the previous cycle, the Core asserts lt_hdata_xfern to the back-end ...
Page 112
... Phase Quad Word Aligned If the PCI master is still ready to receive data, it keeps irdyn asserted and drives the next byte enables (Byte Enable 3) on cben[3:0]. It signals the end of the burst when it de-asserts framen. If the back-end keeps lt_rdyn asserted for the previous two cycles, the Core keeps trdyn asserted and puts Data 3 on ad[31:0] ...
Page 113
... Table 2-44 illustrate a burst transaction to a 32-bit PCI IP core with a 64-bit Local Interface. The figure shows how the PCI interface correlates to the Local Interface. The table gives a clock-by-clock description of each event illustrated in the figure. Figure 2-39. 32-bit Target Burst Write Transaction With a 64-bit Local Interface ...
Page 114
... Phase 1 Address The master asserts framen and drives ad[31:0] and cben[3:0]. The PCI master drives the first byte enable (Byte Enable 1) on cben[3:0 ready to write 2 Wait data, it asserts irdyn and drives the first DWORD (Data 1) on ad[31:0].The Core starts to decode the address and command. It drives the lt_address_out to the back-end. ...
Page 115
... Dual Address Cycle (DAC) The PCI master uses a Dual Address Cycle (DAC) to inform the PCI IP core, operating as a target, that it is using 64-bit addressing with two back-to-back address phases. The PCI IP core can respond to 64-bit addressing when the memory address being accessed is over the 4GB limit ...
Page 116
... Don’t care IPUG18_09.2, November 2010 Don’t care Byte Enable 1 Don’t care Data 1 116 Functional Description Data 1 Data 2 Data 3 0x01 0x00 Data 2 Data 3 Don’t care Address PCI IP Core User’s Guide 12 ...
Page 117
... The Core relinquishes devseln and trdyn. Fast Back-to-Back Transactions The PCI IP core target, can respond to a fast back-to-back transaction if a PCI master wants to perform two or more consecutive transactions to the PCI IP core. The fast back-to-back transaction consists of two or more com- plete PCI transactions without an idle state between them ...
Page 118
... Data 1 is valid. With lt_data_xfern asserted the back-end can safely write Data 1. The PCI master drives the first byte enables (Byte Enable 1) on cben[3:0]. If the master is ready to write data, it asserts irdyn and drives the first DWORD (Data 1) on ad[31:0]. ...
Page 119
... If both irdyn and trdyn are asserted on the previous cycle, the master relinquishes control of 12 Termination framen, ad[31:0] and cben[3:0]. It also de-asserts irdyn if both trdyn and irdyn were asserted last cycle. 13 Idle The Core relinquishes devseln and trdyn. IPUG18_09.2, November 2010 Functional Description Description 119 PCI IP Core User’s Guide ...
Page 120
... Configuration Space read transactions Don’t care Byte Enable 1 Address Don’t care Parity Don’t care Byte Enable 1 Bus Command 120 Functional Description Data 1 Data Parity 1 Data 1 Don’t care Don’t care Address PCI IP Core User’s Guide 9 ...
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... The Core also signals to the back-end that the trans- action is complete by clearing new_cap_hit. The Core de-asserts lt_data_xfern. 8 Idle The Core relinquishes devseln and trdyn. Advanced Configuration Space write accesses are similar to the 32-bit target write transactions with additional PCI and Local bus signals. Figure 2-43 IPUG18_09.2, November 2010 Description ...
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... Don’t care lt_command_out[3:0] Don’t care IPUG18_09.2, November 2010 Data 1 Byte Enable 1 Address Data Parity 1 Parity Don’t care Byte Enable 1 Address Bus Command 122 Functional Description Data 1 Don’t care Don’t care PCI IP Core User’s Guide ...
Page 123
... Local Interface. Table 2-49 In order to prevent a PCI IP core from monopolizing the PCI bus, the PCI Local Bus Specification, Revision 3.0 includes limitations on the amount of transferring time for a target. During the initial data phase, the target must issue a Retry if it cannot respond within 16 clocks of framen being asserted. For subsequent data phases follow- ing the initial data phase, the PCI IP core must respond within eight clock cycles or issue a Disconnect Without Data or a Target Abort ...
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... Once the current data phase is completed, the bus transaction is terminated with a Disconnect With Data. Data on a read transaction. Below is a list of the reasons for the PCI IP core to perform a Disconnect With Data: • Target is slow to complete subsequent data phase • Target does not support requested burst mode • ...
Page 125
... Because the target cannot complete any more PCI data phases, the lt_disconnectn signal is also driven low. The lt_data_xfern signal is driven low by the PCI IP core to the back-end to indicate that data in available on 5 l_ad_in. The trdyn and stopn signals are driven low because both lt_rdyn and lt_disconnectn were driven low 6 during the previous two clock cycles ...
Page 126
... Lattice Semiconductor Table 2-50. 32-bit Target Disconnect with Data for Read Transaction (Continued) CLK De-asserting irdyn disconnects the PCI master. De-asserting devseln and stopn. Disconnects the PCI IP 8 core from the PCI bus. 9 The larger relinquishes devseln, stopn and trdyn. Figure 2-45 and Table 2-51 illustrate a Disconnect With Data on a write transaction ...
Page 127
... Table 2-51. 32-bit Target Disconnect with Data for Write Transaction CLK The devseln signal is driven low to indicate that the PCI IP core has been selected for the transaction. The 4 lt_rdyn signal is driven low to indicate that the back-end application is ready to receive data. Because the tar- get can not complete any more PCI data phases the lt_disconnectn signal is also driven low ...
Page 128
... Table 2-52. 32-bit Target Disconnect Without Data for Read Transaction CLK The devseln signal is driven low to indicate that the PCI IP core is selected for the transaction. The lt_rdyn 4 signal is driven low to indicate that the back-end application is ready to provide data on the next clock cycle. ...
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... Table 2-53. 32-bit Target Disconnect Without Data for Write Transaction CLK Description The devseln signal is driven low to indicate that the PCI IP core is selected for the transaction. The lt_rdyn 4 signal is driven low to indicate that the back-end application is ready to receive data. The trdyn signal is driven low because the lt_rdyn signal was driven low on the previous clock cycle. ...
Page 130
... Lattice Semiconductor Retry A Retry may be necessary if the PCI IP core cannot assert the trdyn signal within the maximum number of clock cycles defined by the PCI Local Bus Specification, Revision 3.0. A Retry occurs if lt_rdyn is not asserted before lt_disconnectn is asserted. A Retry can also occur if the PCI IP core does not assert lt_rdyn within 16 clocks after the assertion of framen ...
Page 131
... Lattice Semiconductor Table 2-54. 32-bit Target Retry for Read Transaction CLK The devseln signal is driven low to indicate that the PCI IP core is selected for the transaction. The lt_rdyn signal remains high to indicate that the back-end application is not ready to provide data. Because the target can 4 not complete any PCI data phases, the lt_rdyn signal remains high and the lt_disconnectn signal is driven low ...
Page 132
... Don’t care Table 2-55. 32-bit Target Retry for Write Transaction CLK The devseln signal is driven low to indicate that the PCI IP core is selected for the transaction. The lt_rdyn signal remains high to indicate that the back-end application is not ready to provide data. Because the target can 4 not complete any PCI data phases, the lt_rdyn signal remains high and the lt_disconnectn signal is driven low ...
Page 133
... Lattice Semiconductor Table 2-55. 32-bit Target Retry for Write Transaction (Continued) CLK The PCI master terminates the transaction by de-asserting the irdyn. The PCI IP core de-asserts the devseln 8 and stopn. 9 Idle Target Abort Unlike the other types of disconnects, the state of Abort. Figure 2-50 illustrates a Target Abort during a read transaction. ...
Page 134
... The lt_data_xfern signal is driven low by the PCI IP core to the back-end to indicate that data on l_ad_in is 5 being read.The lt_rdyn signal is driven low to indicate the back-end is ready to provide the next data. ...
Page 135
... Lattice Semiconductor Table 2-57. 32-bit Target Abort for Write Transaction CLK The devseln signal is driven low to indicate that the PCI IP core is selected for the transaction. The lt_rdyn 4 signal is driven low to indicate that the back-end application is ready to receive data on the next two cycles. ...
Page 136
... Core Generation” on page 143 Table 3-1 provides the list of user configurable parameters for the PCI IP core. The parameter settings are specified using the PCI IP core Configuration GUI in IPexpress. The numerous PCI Express parameter options are parti- tioned across multiple GUI tabs as shown in this chapter. ...
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... The address and data width on the PCI side. Local Master Data Bus Size (Master/Target cores only) The data width for Local Master read/write transactions, must be the same as the PCI Data Bus Size. Local Target Data Bus Size (Master/Target cores only) The data width for Local Target read/write transactions, must be the same as the PCI Data Bus Size. ...
Page 138
... The address width for Local Master and Target read/write transactions, must be the same as the PCI Data Bus Size. Bus Speed PCI bus operation frequency. A clock frequency on the PCI side. A fixed value that depends on the PCI core being used. Backend Configuration Enable Backend Configuration When this option is selected, the core works independently by configuring in the backend ...
Page 139
... Lattice Semiconductor Identification Tab Figure 3-2 shows the contents of the Identification tab. This example shows the PCI Master/Target 33. Figure 3-2. Identification Tab Vendor ID [15:0] The Vendor 16-bit parameter used to identify the manufacturer of the product. The Vendor ID is assigned by the PCI SIG to ensure uniqueness. ...
Page 140
... When Read Only is selected, the Expansion ROM base address is specified by the Read Only Address parameter and can only be read by other PCI devices. When Read Only is not selected, the Expansion ROM base address can be specified by another PCI master device via the PCI bus. ...
Page 141
... A mechanism for ensuring that a bus master does not extend the access latency of other masters beyond a speci- fied value. MIN_GNT An 8-bit parameter used to specify the length of time in microseconds for the Master to control the PCI bus. MAX_LAT An 8-bit parameter used to specify how often the PCI Core possess the bus. ...
Page 142
... Used to map memory or I/O space. Address Space Size The parameter is the size of the address range mapped to memory or I/O space. Prefetching Enable This option determines if the memory mapped by this BAR support prefetching operation. IPUG18_09.2, November 2010 142 Parameter Settings PCI IP Core User’s Guide ...
Page 143
... Getting Started The PCI IP core is available for download from the Lattice IP Server using the IPexpress tool. The IP files are auto- matically installed using ispUPDATE technology in any customer-specified directory. After the IP core has been installed, the IP core will be available in the IPexpress GUI dialog box shown in ...
Page 144
... Device Family and Part Name default to the specified project parameters. Refer to the IPexpress tool online help for further information. To create a custom configuration, the user clicks the Customize button in the IPexpress tool dialog box to display the PCI IP core Configuration GUI, as shown in eter options specific to their application. Refer to IP core parameter settings. ...
Page 145
... Lattice Semiconductor Figure 4-2. Configuration GUI (Diamond Version) IPUG18_09.2, November 2010 145 IP Core Generation PCI IP Core User’s Guide ...
Page 146
... When the user clicks the Generate button in the IP Configuration dialog box, the IP core and supporting files are generated in the specified “Project Path” directory. The directory structure of the generated files is shown in Figure 4-3. This example shows the directory structure generated with the PCI Master/Target 33 for LatticeECP3 device. Figure 4-3. PCI IP Core Directory Structure Table 4-1 provides a list of key files and directories created by the IPexpress tool and how they are used ...
Page 147
... Running Functional Simulation Simulation support for the PCI IP core is provided for Aldec Active-HDL (Verilog and VHDL) simulator and Mentor Graphics ModelSim (Verilog only) simulator. The functional simulation includes a PCI bus stimulus module (pci_stim_tb) and a local module (lt_stim_tb), which is instantiated in a top level (pci_testbench_top) ...
Page 148
... Number of errors: 0 >> Synthesizing and Implementing the Core in a Top-Level Design Synthesis support for the PCI IP core is provided for Mentor Graphics Precision or Synopsys Synplify. The PCI IP core itself is synthesized and is provided in NGO format when the core is generated in IPexpress. Users may syn- thesize the core in their own top-level design by instantiating the core in their top-level as described previously and then synthesizing the entire design with either Synplify or Precision RTL synthesis ...
Page 149
... The Select Target Core Version, Design Entry, and Device dialog box shows the current settings for the IP core in the Source Value box. Make your new settings in the Target Value box. IPUG18_09.2, November 2010 149 IP Core Generation PCI IP Core User’s Guide ...
Page 150
... As the options change, the schematic diagram of the IP core changes to show the I/O and the device resources the IP core will need. 7. Click Generate. 8. Click the Generate Log tab to check for warnings and error messages. IPUG18_09.2, November 2010 150 IP Core Generation PCI IP Core User’s Guide ...
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... Local Support Contact your nearest Lattice Sales Office. Internet www.latticesemi.com PCI-SIG Website The Peripheral Component Interconnect Special Interest Group (PCI-SIG) website contains specifications and doc- uments referred to in this user's guide. The PCi-SIG URL is: http://www.pcisig.com. References LatticeEC/ECP • ...
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... Added Parameter Descriptions section. 5.2 Updated appendices. Added LatticeECP2M appendix. 5.2 Updated references to PCI Local Bus Specification from revision 2.2 to revision 3.0. Updated Command Register figure and table. Replaced “stepping control” with “reserved bit”. 5.2 Updated BAR Mapped to Memory Space section. Updated command9:0 signal description in the Local Interface Signals table ...
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... LatticeECP/EC family. Ordering Part Number Table A-2 lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for Lat- ticeECP/EC. Table A-2. OPN for LatticeECP/EC PCI IP Core Speed ...
Page 154
... LatticeECP2 family. Ordering Part Number Table A-4 lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for LatticeECP2. Table A-4. OPN for LatticeECP2 PCI IP Core ...
Page 155
... LatticeECP2M family. Ordering Part Number Table A-6 lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for LatticeECP2M. Table A-6. OPN for LatticeECP2M PCI IP Core ...
Page 156
... LatticeECP3 family. Ordering Part Number Table A-8 lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for LatticeECP3. Table A-8. OPN for LatticeECP3 PCI IP Core ...
Page 157
... LatticeXP family. Ordering Part Number Table A-10 lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for Lat- ticeXP. Table A-10. OPN for LatticeXP PCI IP Core ...
Page 158
... LatticeXP2 family. Ordering Part Number Table A-12 lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for LatticeXP2. Table A-12. OPN for LatticeXP2 PCI IP Core ...
Page 159
... MachXO family. Ordering Part Number Table A-14 lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for MachXO. Table A-14. MachXO OPN for PCI IP Core ...
Page 160
... LatticeSC family. Ordering Part Number Table A-18 lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for Lat- ticeSC. Table A-18. OPN for LatticeSC PCI IP Core ...
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... Pin Assignment Considerations for LatticeECP and LatticeEC Devices PCI Pin Assignments for Master/Target 33MHz 64-Bit Bus The PCI Master/Target 33MHz 64-bit core is optimized for LFEC33E-5F672C. An example assignment, optimized for best performance, is given in Table contained with the .lpf preference file. Refer to the readme file included with the core package for further informa- tion ...
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... Lattice Semiconductor Table B-1. PCI Pins Assignments (Continued) IPUG18_09.2, November 2010 Pin Assignments For Lattice FPGAs Signal Name Pin/Bank Buffer Type ad[30] AF3/5 PCI33_BIDI ad[31] AE2/5 PCI33_BIDI ad[32] AF24/4 PCI33_BIDI ad[33] AF23/4 PCI33_BIDI ad[34] AE23/4 PCI33_BIDI ad[35] AF22/4 PCI33_BIDI ad[36] AE22/4 PCI33_BIDI ad[37] AF21/4 PCI33_BIDI ad[38] AE21/4 PCI33_BIDI ad[39] AF20/4 PCI33_BIDI ad[40] AE20/4 ...
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... Lattice Semiconductor Table B-1. PCI Pins Assignments (Continued) PCI Pin Assignments for Target 66MHz 64-Bit Bus The PCI Target 33MHz 64-bit core is optimized for LFEC33E-5F672C. An example pin assignment, optimized for best performance, is given in Table tion. Table B-2. PCI Pins Assignments IPUG18_09.2, November 2010 ...
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... Lattice Semiconductor Table B-2. PCI Pins Assignments (Continued) IPUG18_09.2, November 2010 Pin Assignments For Lattice FPGAs Signal Name Pin/Bank I/O Type ad[17] AE7/5 PCI33_BIDI ad[18] AF7/5 PCI33_BIDI ad[19] AC6/5 PCI33_BIDI ad[20] AD6/5 PCI33_BIDI ad[21] AE6/5 PCI33_BIDI ad[22] AF6/5 PCI33_BIDI ad[23] AC5/5 PCI33_BIDI ad[24] AD5/5 PCI33_BIDI ad[25] AE5/5 PCI33_BIDI ad[26] AF5/5 PCI33_BIDI ad[27] AE4/5 PCI33_BIDI ...
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... Lattice Semiconductor Table B-2. PCI Pins Assignments (Continued) PCI Pin Assignments for Master/Target 33MHz 32-Bit Bus The PCI Master/Target 33MHz 32-bit core is optimized for LFEC33E-5F672C. An example pin assignment, opti- mized for best performance, is given in ther information. Table B-3. PCI Pins Assignments IPUG18_09.2, November 2010 ...
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... Lattice Semiconductor Table B-3. PCI Pins Assignments (Continued) IPUG18_09.2, November 2010 Pin Assignments For Lattice FPGAs Signal Name Pin/Bank Buffer Type ad[7] AA8/5 PCI33_BIDI ad[8] AB8/5 PCI33_BIDI ad[9] AC8/5 PCI33_BIDI ad[10] AD8/5 PCI33_BIDI ad[11] AE8/5 PCI33_BIDI ad[12] AF8/5 PCI33_BIDI ad[13] AA7/5 PCI33_BIDI ad[14] AB7/5 PCI33_BIDI ad[15] AC7/5 PCI33_BIDI ad[16] AD7/5 PCI33_BIDI ad[17] AE7/5 ...
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... Lattice Semiconductor PCI Pin Assignments for Target 33MHz 32-Bit Bus The PCI Target 33MHz 32-bit core is optimized for LFEC33E-5F672C. An example pin assignment, optimized for best performance, is given in Table tion. Table B-4. PCI Pins Assignments IPUG18_09.2, November 2010 B-4. Refer to the readme file included with the core package for further informa- ...
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... Table B-4. PCI Pins Assignments (Continued) Pin Assignment Considerations for LatticeXP Devices PCI Pin Assignments for Master/Target 33MHz 32-Bit Bus The PCI Master/Target 33MHz 32-bit core is optimized for LFXP10-4F388C. An example pin assignment, opti- mized for best performance, is given in ther information. Table B-5. PCI Pins Assignments IPUG18_09 ...
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... Table B-5. PCI Pins Assignments (Continued) PCI Pin Assignments for Target 33MHz 32-Bit Bus The PCI Target 33MHz 32-bit core is optimized for LFXP10-4F388C. An example pin assignment, optimized for best performance, is given in Table 63. Refer to the readme file included with the core package for further informa- tion ...
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... Lattice Semiconductor Table B-6. PCI Pins Assignments (Continued) IPUG18_09.2, November 2010 Signal Name Pin/Bank Buffer Type ad[1] AA18/4 PCI33_BIDI ad[2] Y18/4 PCI33_BIDI ad[3] AB17/4 PCI33_BIDI ad[4] Y14/4 PCI33_BIDI ad[5] Y13/4 PCI33_BIDI ad[6] AA17/4 PCI33_BIDI ad[7] Y17/4 PCI33_BIDI ad[8] AB16/4 PCI33_BIDI ad[9] AA16/4 PCI33_BIDI ad[10] AB15/4 PCI33_BIDI ad[11] AA15/4 PCI33_BIDI ad[12] W13/4 PCI33_BIDI ad[13] W12/4 PCI33_BIDI ...
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... Lattice Semiconductor Table B-6. PCI Pins Assignments (Continued) PCI Pin Assignments for Master/Target 33MHz 64-Bit Bus The PCI Master/Target 33MHz 64-bit core is optimized for LFXP20C-4F484C. An example pin assignment, opti- mized for best performance, is given in ther information. Table B-7. PCI Pin Assignments IPUG18_09.2, November 2010 ...
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... Lattice Semiconductor Table B-7. PCI Pin Assignments (Continued) IPUG18_09.2, November 2010 Pin Assignments For Lattice FPGAs Signal Name Pin/Bank Buffer Type ad(28) AB5 / 5 PCI33_BIDI ad(29) AA4 / 5 PCI33_BIDI ad(30) AB4 / 5 PCI33_BIDI ad(31) AA3 / 5 PCI33_BIDI ad(32) AA21 / 4 PCI33_BIDI ad(33) AB20 / 4 PCI33_BIDI ad(34) AA20 / 4 PCI33_BIDI ad(35) Y20 / 4 PCI33_BIDI ad(36) AB19 / 4 PCI33_BIDI ad(37) AA19 / 4 PCI33_BIDI ad(38) Y19 / 4 ...
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... Table B-7. PCI Pin Assignments (Continued) Pin Assignment Considerations for MachXO Devices PCI Pin Assignments for Target 33MHz 32-Bit Bus The PCI Target 33MHz 32-bit core is optimized for LCMXO1200C-4FT256C. An example pin assignment, opti- mized for best performance, is given in ther information. Table B-8. PCI Pin Assignments IPUG18_09 ...
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... Lattice Semiconductor Table B-8. PCI Pin Assignments (Continued) IPUG18_09.2, November 2010 Pin Assignments For Lattice FPGAs Signal Name Pin/Bank Buffer Type ad(12 PCI33_BIDI ad(13 PCI33_BIDI ad(14 PCI33_BIDI ad(15 PCI33_BIDI ad(16 PCI33_BIDI ad(17 PCI33_BIDI ad(18 PCI33_BIDI ad(19 PCI33_BIDI ad(20 PCI33_BIDI ad(21 PCI33_BIDI ad(22 PCI33_BIDI ...
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... Lattice Semiconductor PCI Pin Assignments for Target 66MHz 32-Bit Bus The PCI Target 66MHz 32-bit core is optimized for LCMXO1200C-4FT256C. An example pin assignment, opti- mized for best performance, is given in ther information. Table B-9. PCI Pin Assignments IPUG18_09.2, November 2010 Table B-9. Refer to the readme file included with the core package for fur- ...
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... Lattice Semiconductor Table B-9. PCI Pin Assignments (Continued) PCI Pin Assignments for Master/Target 33MHz 32-Bit Bus The PCI Master/Target 33MHz 32-bit core is optimized for LCMXO2280C-5FT324C. An example pin assignment, optimized for best performance, is given in further information. Table B-10. PCI Pin Assignments IPUG18_09.2, November 2010 ...
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... Lattice Semiconductor Table B-10. PCI Pin Assignments (Continued) IPUG18_09.2, November 2010 Signal Name Pin/Bank ad(17 ad(18) E10 / 1 ad(19) C10 / 1 ad(20) B11 / 1 ad(21) A11 / 1 ad(22) F10 / 1 ad(23) D10 / 1 ad(24) C11 / 1 ad(25) A12 / 1 ad(26) E11 / 1 ad(27) D11 / 1 ad(28) C12 / 1 ad(29) B12 / 1 ad(30) B13 / 1 ad(31) A13 / 1 cben(0) D12 / 1 cben(1) A15 / 1 cben(2) B14 / 1 cben(3) B16 / 1 par A14 / 1 PCI Interface Controls ...
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... Lattice Semiconductor PCI Assignment Considerations for LatticeSC Devices PCI Pin Assignments for Master/Target 33 MHz 32-bit Bus The PCI Master/Target 33 MHz 32-bit core is optimized for LFSC3GA25E-5F900C. An example pin assignment, optimized for best performance, is given in further information. Table B-11. PCI Pin Assignments IPUG18_09.2, November 2010 Table B-11 ...
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... Lattice Semiconductor Table B-11. PCI Pin Assignments (Continued) PCI Pin Assignments for Master/Target 33 MHz 64-bit Bus The PCI Master/Target 33 MHz 64-bit core is optimized for LFSC3GA25E-5F900C. An example pin assignment, optimized for best performance, is given in further information. Table B-12. PCI Pin Assignments IPUG18_09.2, November 2010 ...
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... Lattice Semiconductor Table B-12. PCI Pin Assignments (Continued) IPUG18_09.2, November 2010 Pin Assignments For Lattice FPGAs Signal Name Pin/Bank ad[14] AE10/5 ad[15] AF9/5 ad[16] AJ3/5 ad[17] AH3/5 ad[18] AG8/5 ad[19] AF8/5 ad[20] AG5/5 ad[21] AH4/5 ad[22] AF6/5 ad[23] AF7/5 ad[24] AD8/5 ad[25] AD7/5 ad[26] AK2/5 ad[27] AJ2/5 ad[28] AD6/5 ad[29] AH2/5 ad[30] AG3/5 ad[31] AE5/5 ad[32] AK23/4 ad[33] AK22/4 ad[34] AF19/4 ad[35] AG19/4 ad[36] AJ21/4 ...
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... Lattice Semiconductor Table B-12. PCI Pin Assignments (Continued) IPUG18_09.2, November 2010 Signal Name Pin/Bank ad[55] AK17/4 ad[56] AK16/4 ad[57] AK15/5 ad[58] AK14/5 ad[59] AJ15/5 ad[60] AJ14/5 ad[61] AK13/5 ad[62] AK12/5 ad[63] AE15/5 cben[0] AH10/5 cben[1] AH11/5 cben[2] AF13/5 cben[3] AE14/5 cben[4] AG15/5 cben[5] AH12/5 cben[6] AJ13/5 cben[7] AD15/5 par AG14/5 par64 ...
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... Lattice Semiconductor PCI Pin Assignments for Target 33 MHz 32-bit Bus The PCI Target 33 MHz 32-bit core is optimized for LFSC3GA25E-5F900C. An example pin assignment, optimized for best performance, is given in information. Table B-13. PCI Pin Assignments IPUG18_09.2, November 2010 Table B-13. Refer to the readme file included with the core package for further ...
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... Lattice Semiconductor Table B-13. PCI Pin Assignments (Continued) PCI Pin Assignments for Target 33 MHz 64-bit Bus The PCI Target 33 MHz 64-bit core is optimized for LFSC3GA25E-5F900C. An example pin assignment, optimized for best performance, is given in information. Table B-14. PCI Pin Assignments IPUG18_09.2, November 2010 Signal Name ...
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... Lattice Semiconductor Table B-14. PCI Pin Assignments (Continued) IPUG18_09.2, November 2010 Pin Assignments For Lattice FPGAs Signal Name Pin/Bank ad[20] AG5/5 ad[21] AH4/5 ad[22] AF6/5 ad[23] AF7/5 ad[24] AD8/5 ad[25] AD7/5 ad[26] AK2/5 ad[27] AJ2/5 ad[28] AD6/5 ad[29] AH2/5 ad[30] AG3/5 ad[31] AE5/5 ad[32] AK23/4 ad[33] AK22/4 ad[34] AF19/4 ad[35] AG19/4 ad[36] AJ21/4 ad[37] AJ20/4 ad[38] AG18/4 ad[39] AF18/4 ad[40] AK20/4 ad[41] AJ19/4 ad[42] AJ18/4 ...
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... Lattice Semiconductor Table B-14. PCI Pin Assignments (Continued) PCI Pin Assignments for Master/Target 66 MHz 32-bit Bus The PCI Master/Target 66 MHz 32-bit core is optimized for LFSC3GA25E-5F900C. An example pin assignment, optimized for best performance, is given in further information. Table B-15. PCI Pin Assignments IPUG18_09.2, November 2010 ...
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... Lattice Semiconductor Table B-15. PCI Pin Assignments (Continued) IPUG18_09.2, November 2010 Signal Name Pin/Bank ad[10] AF10/5 ad[11] AE11/5 ad[12] AJ4/5 ad[13] AK3/5 ad[14] AE10/5 ad[15] AF9/5 ad[16] AJ3/5 ad[17] AH3/5 ad[18] AG8/5 ad[19] AF8/5 ad[20] AG5/5 ad[21] AH4/5 ad[22] AF6/5 ad[23] AF7/5 ad[24] AD8/5 ad[25] AD7/5 ad[26] AK2/5 ad[27] AJ2/5 ad[28] AD6/5 ad[29] AH2/5 ad[30] AG3/5 ad[31] AE5/5 cben[0] AH10/5 cben[1] AH11/5 cben[2] AF13/5 ...
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... Lattice Semiconductor PCI Pin Assignments for Master/Target 66 MHz 64-bit Bus The PCI Master/Target 66 MHz 64-bit core is optimized for LFSC3GA25E-5F900C. An example pin assignment, optimized for best performance, is given in further information. Table B-16. PCI Pin Assignments IPUG18_09.2, November 2010 Table B-16. Refer to the readme file included with the core package for ...
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... Lattice Semiconductor Table B-16. PCI Pin Assignments (Continued) IPUG18_09.2, November 2010 Signal Name Pin/Bank ad[35] AG19/4 ad[36] AJ21/4 ad[37] AJ20/4 ad[38] AG18/4 ad[39] AF18/4 ad[40] AK20/4 ad[41] AJ19/4 ad[42] AJ18/4 ad[43] AG17/4 ad[44] AF17/4 ad[45] AH18/4 ad[46] AH17/4 ad[47] AK19/4 ad[48] AK18/4 ad[49] AG16/4 ad[50] AH16/4 ad[51] AF16/4 ad[52] AE16/4 ad[53] AJ17/4 ad[54] AJ16/4 ad[55] AK17/4 ad[56] AK16/4 ad[57] AK15/5 ad[58] AK14/5 ad[59] AJ15/5 ad[60] AJ14/5 ad[61] AK13/5 ad[62] AK12/5 ...
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... Lattice Semiconductor Table B-16. PCI Pin Assignments (Continued) PCI Pin Assignments for Target 66 MHz 32-bit Bus The PCI Target 66 MHz 32-bit core is optimized for LFSC3GA25E-5F900C. An example pin assignment, optimized for best performance, is given in information. Table B-17. PCI Pin Assignments IPUG18_09.2, November 2010 Signal Name ...
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... Lattice Semiconductor Table B-17. PCI Pin Assignments (Continued) IPUG18_09.2, November 2010 Pin Assignments For Lattice FPGAs Signal Name Pin/Bank ad[22] AF6/5 ad[23] AF7/5 ad[24] AD8/5 ad[25] AD7/5 ad[26] AK2/5 ad[27] AJ2/5 ad[28] AD6/5 ad[29] AH2/5 ad[30] AG3/5 ad[31] AE5/5 ad[32] AK23/4 ad[33] AK22/4 ad[34] AF19/4 ad[35] AG19/4 ad[36] AJ21/4 ad[37] AJ20/4 ad[38] AG18/4 ad[39] AF18/4 ad[40] AK20/4 ad[41] AJ19/4 ad[42] AJ18/4 ad[43] AG17/4 ad[44] AF17/4 ...
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... Lattice Semiconductor Table B-17. PCI Pin Assignments (Continued) PCI Pin Assignments for Target 66 MHz 64-bit Bus The PCI Target 66 MHz 64-bit core is optimized for LFSC3GA25E-5F900C. An example pin assignment, optimized for best performance, is given in information. Table B-18. PCI Pin Assignments IPUG18_09.2, November 2010 Signal Name ...
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... Lattice Semiconductor Table B-18. PCI Pin Assignments (Continued) IPUG18_09.2, November 2010 Pin Assignments For Lattice FPGAs Signal Name Pin/Bank ad[9] AH7/5 ad[10] AF10/5 ad[11] AE11/5 ad[12] AJ4/5 ad[13] AK3/5 ad[14] AE10/5 ad[15] AF9/5 ad[16] AJ3/5 ad[17] AH3/5 ad[18] AG8/5 ad[19] AF8/5 ad[20] AG5/5 ad[21] AH4/5 ad[22] AF6/5 ad[23] AF7/5 ad[24] AD8/5 ad[25] AD7/5 ad[26] AK2/5 ad[27] AJ2/5 ad[28] AD6/5 ad[29] AH2/5 ad[30] AG3/5 ad[31] AE5/5 ...
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... Lattice Semiconductor Table B-18. PCI Pin Assignments (Continued) IPUG18_09.2, November 2010 Signal Name Pin/Bank ad[53] AJ17/4 ad[54] AJ16/4 ad[55] AK17/4 ad[56] AK16/4 ad[57] AK15/5 ad[58] AK14/5 ad[59] AJ15/5 ad[60] AJ14/5 ad[61] AK13/5 ad[62] AK12/5 ad[63] AE15/5 cben[0] AH10/5 cben[1] AH11/5 cben[2] AF13/5 cben[3] AE14/5 cben[4] AG15/5 cben[5] AH12/5 cben[6] AJ13/5 cben[7] AD15/5 par ...