PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 28

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
Table 2-10. Customer Specific Parameters (Continued)
IPUG18_09.2, November 2010
pci_66mhz_
cap_p
bar_64b_dat_
bus_p
bar0_p
bar1_ p
bar2_ p
bar3_ p
bar4_ p
bar5_ p
Configuration
Port Inputs
Space
1
1
1
1
1
1
PCI_66MHZ_CAP_g
BAR_64BIT_DATA_BUS_g
BAR0_g
BAR1_g
BAR2_g
BAR3_g
BAR4_g
BAR5_g
Corresponding Parameter
Name in PCI_params.v
1
1
1
1
1
1
0 - 0xFFFFFFFF 0x00000000
0 - 0xFFFFFFFF 0x00000000
0 - 0xFFFFFFFF 0x00000000
0 - 0xFFFFFFFF 0x00000002
0 - 0xFFFFFFFF 0x00000002
0 - 0xFFFFFFFF 0x00000002
6’b000000 -
6’b111111
33 or 66
Range
28
6’b000000
Default
66
PCI value for the Status field bit to enable
66MHz. This is bit 5 in the status register. A 1
indicates that the PCI IP core is 66MHZ
capable, and a 0 indicates that it is not. The
default value is 1.
For 32-bit Local Data bus this parameter
value is 6'b000000. For 64-bit Local Data bus
this parameter value is 6'b111111.
BAR0 configuration parameter (lower half of
a 64-bit BAR). The lower four bits are used
for BAR definition as indicated in the PCI
specification. Rest of the bits indicate the
memory or I/O size supported This BAR is
located at 10h. If the bar is not used, it should
be 32’h00000002.
BAR1 configuration parameter (upper half of
a 64-bit BAR). The lower four bits are used
for BAR definition as indicated in the PCI
specification. Rest of the bits indicate the
memory or I/O size supported This BAR is
located at 14h. If the bar is not used, it should
be 32’h00000002.
BAR2 configuration parameter (lower half of
a 64-bit BAR). The lower four bits are used
for BAR definition as indicated in the PCI
specification. Rest of the bits indicate the
memory or I/O size supported This BAR is
located at 18h. If the bar is not used, it should
be 32’h00000002.
BAR3 configuration parameter (upper half of
a 64-bit BAR). The lower four bits are used
for BAR definition as indicated in the PCI
specification. Rest of the bits indicate the
memory or I/O size supported This BAR is
located at 1Ch. If the bar is not used, it
should be 32’h00000002.
BAR4 configuration parameter (lower half of
a 64-bit BAR). The lower four bits are used
for BAR definition as indicated in the PCI
specification. Rest of the bits indicate the
memory or I/O size supported This BAR is
located at 20h. If the bar is not used, it should
be 32’h00000002.
BAR5 configuration parameter (upper half of
a 64-bit BAR). The lower four bits are used
for BAR definition as indicated in the PCI
specification. Rest of the bits indicate the
memory or I/O size supported This BAR is
located at 24h. If the bar is not used, it should
be 32’h00000002.
Functional Description
Description
PCI IP Core User’s Guide