PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 148

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Synthesizing and Implementing the Core in a Top-Level Design
Synthesis support for the PCI IP core is provided for Mentor Graphics Precision or Synopsys Synplify. The PCI IP
core itself is synthesized and is provided in NGO format when the core is generated in IPexpress. Users may syn-
thesize the core in their own top-level design by instantiating the core in their top-level as described previously and
then synthesizing the entire design with either Synplify or Precision RTL synthesis.
The top-level file <username>_eval_top.v provided in 
\<project_dir>\pci_master_target_eval\<username>\src\top
supports the ability to implement the PCI Express core in isolation. Push-button implementation of this top-level
design with either Synplify or Precision RTL Synthesis is supported via the project files 
<username>_eval.ldf (Diamond) or .syn (ispLEVER) located in the 
\<project_dir>\pci_master_target_eval\<username>\impl\synplify
and the 
\<project_dir>\pci_master_target_eval\<username>\impl\precision directories, respectively.
To use this project file in Diamond:
1. Choose File > Open > Project.
2. Browse to \<project_dir>\pci_master_target_eval\<username>\impl\(synplify or preci-
3. Select and open <username>.ldf. At this point, all of the files needed to support top-level synthesis and imple-
4. Select the Process tab in the left-hand GUI window.
5. Implement the complete design via the standard Diamond GUI flow.
To use this project file in ispLEVER:
1. Choose File > Open Project.
2. Browse to \<project_dir>\pci_master_target_eval\<username>\impl\(synplify or preci-
3. Select and open <username>.syn. At this point, all of the files needed to support top-level synthesis and imple-
4. Select the device top-level entry in the left-hand GUI window.
5. Implement the complete design via the standard ispLEVER GUI flow.
Hardware Evaluation
The PCI IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of
the IP core that operate in hardware for a limited period of time (approximately four hours) without requiring the pur-
chase of an IP license. It may also be used to evaluate the core in hardware in user-defined designs.
Enabling Hardware Evaluation in Diamond
Choose Project > Active Strategy > Translate Design Settings. The hardware evaluation capability may be
enabled/disabled in the Strategy dialog box. It is enabled by default.
<< Number of errors: 0 >>
sion) in the Open Project dialog box.
mentation will be imported to the project.
sion) in the Open Project dialog box.
mentation will be imported to the project.
148
PCI IP Core User’s Guide
IP Core Generation