PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 35

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
Table 2-12. 32-bit Master Single Write Transaction with a 32-bit Local Interface
IPUG18_09.2, November 2010
64-Bit PCI Master with a 64-Bit Local Bus
This section discusses read and write transactions for a PCI IP core configured with a 64-bit PCI bus and a 64-bit
local bus. The PCI Specification requires all 64-bit PCI master devices to execute both 64-bit and 32-bit transac-
tions. The 32-bit transactions for the 32-bit Core, described in the previous section, are similar to the 32-bit transac-
tions for the 64-bit PCI IP core configuration.
The 64-bit memory read transaction is similar to the 32-bit memory read transaction with the exception of additional
PCI signals required for 64-bit signaling.
CLK
10
1
2
3
4
5
6
7
8
9
Turn around
Address
Phase
Data 1
Wait
Idle
Idle
Idle
Idle
Idle
Idle
The lm_req32n signal is asserted by the master application logic on the Local Master interface for
the 32-bit data transaction request. The Local Master interface drives the PCI starting address, the
bus command, and the burst transaction length during the same clock cycle on l_ad_in,
lm_cben_in and lm_burst_length, respectively.
The Core's Local Master Interface detects the asserted lm_req32n and asserts reqn to request
the use of PCI bus.
gntn is asserted to grant the Core access to the PCI bus. Core is now the PCI master.
Since gntn is asserted and the current bus is idle, the Core is going to start the bus transactions.
The Core asserts lm_gntn to inform the local master that the bus request is granted.
If both lm_req32n and gntn were asserted on the previous cycle, lm_status[3:0] is changed
to ‘Address Loading’ to indicate the starting address, the bus command and the burst length are
being latched.
The local master de-asserts lm_req32n when the previous lm_status[3:0] was ‘Address
Loading’ and if it doesn’t want to request another PCI bus transaction.
The Core asserts framen to initiate the 32-bit write transaction when gntn was asserted and
lm_status[3:0] was ‘Address Loading’ on the previous cycle. It also drives the PCI starting
address on ad[31:0] and the PCI command on cben[3:0]. On the same cycle, it outputs
lm_status[3:0] as ‘Bus Transaction’ to indicate the beginning of the address/data phases.
lm_burst_cnt gets the value of the burst length.
Because lm_rdyn was asserted on the previous cycle and the next cycle is the first data phase,
the local master provides Data 1 on l_ad_in[31:0] and the byte enables on
lm_cben_in[3:0]. And the Core asserts lm_data_xfern to the local master to signify these
data and byte enables are being read and will be transferred to the PCI bus.
Asserting lm_rdyn means the local master is ready to write data. If it is not, it keeps lm_rdyn de-
asserted until it is ready.
If the target completes the fast decode and is ready to receive 32-bit data, it asserts devseln and
trdyn.
The Core de-asserts reqn when framen was asserted and lm_req32n was de-asserted on the
previous cycle.
With lm_data_xfern asserted on the previous cycle that was the address phase, the local mas-
ter increments the address counter while the Core transfers Data 1 and the byte enables to
ad[31:0] and cben[3:0].
The Core de-asserts lm_gntn to follow gntn. Since the transaction only has one data, the Core
asserts irdyn and de-asserts framen, Data 1 and the byte enables are kept on the PCI bus, the
first data phase is completed.
The Core relinquishes control of framen, ad and cben. It de-asserts irdyn, decreases
lm_burst_cnt to zero and changes lm_status[3:0] into ‘Bus Termination’ with
lm_termination as ‘Normal Termination’ because both trdyn and irdyn were asserted last
cycle. The target de-asserts devseln, ackn and trdyn.
The Core relinquishes control of irdyn and par.
Figure 2-9
and
35
Table 2-13
Description
illustrate a basic 64-bit read transaction.
Functional Description
PCI IP Core User’s Guide