PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 137

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
Table 3-1. Parameter Descriptions (Continued)
IPUG18_09.2, November 2010
Bus Tab
Figure 3-1
Figure 3-1. Bus Tab
Bus Definition
PCI Data Bus Size
The address and data width on the PCI side.
Local Master Data Bus Size (Master/Target cores only)
The data width for Local Master read/write transactions, must be the same as the PCI Data Bus Size.
Local Target Data Bus Size (Master/Target cores only)
The data width for Local Target read/write transactions, must be the same as the PCI Data Bus Size.
BAR2
BAR3 - BAR5
BAR0 to BAR5 Configuration Options
BAR width
BAR Type
Address Space Size
Prefetching Enable
1. Only for PCI Master/Target Core.
2. Only for PCI Target Core.
shows the contents of the Bus tab. This example shows the PCI Master/Target 33.
Parameter
None, 4 bytes, 8 bytes, ... , 8G
0x 00000000 -
0x 00000000 -
0x FFFFFFFF
0x FFFFFFFF
Memory, I/O
Yes, No
Range
32, 64
137
4 bytes for BAR0 16 bytes for BAR1, BAR2
Memory for BAR1, BAR2
0x FFFFFFF0
I/O for BAR0,
0x 00000000
Default
PCI IP Core User’s Guide
Parameter Settings
No
32