PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 157

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
LatticeXP FPGAs
Table A-9. Performance and Resource Utilization
Ordering Part Number
Table A-10
ticeXP.
Table A-10. OPN for LatticeXP PCI IP Core
Target 33 MHz, 32-bit PCI/
Local/Address bus width
Target 33 MHz, 64-bit PCI/
Local/Address bus width
Target 66 MHz, 32-bit PCI/
Local/Address bus width
Target 66 MHz, 64-bit PCI/
Local/Address bus width
Master/Target 33 MHz, 32-bit PCI/
Local/Address bus width
Master/Target 33 MHz, 64-bit PCI/
Local/Address bus width
Master/Target 66 MHz, 32-bit PCI/
Local/Address bus width
1. Performance and utilization data are generated using an LFXP20C-5F484C device with Lattice Diamond 1.0 software. Performance may
vary when using a different software version or targeting a different device density or speed grade within the LatticeXP family.
User-Configurable Mode
lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for Lat-
IPexpress
33 MHz
33 MHz
66 MHz
66 MHz
33 MHz
33 MHz
66 MHz
66 MHz
Speed
PCI Bus
32-bit
64-bit
32-bit
64-bit
32-bit
64-bit
32-bit
64-bit
SLICEs
1090
1083
586
715
606
832
846
Master/Target
Master/Target
Master/Target
Master/Target
LUTs
1344
1060
1549
1690
1
703
913
966
Target
Target
Target
Target
Type
157
Registers
472
594
493
614
642
849
663
PCI-MT32-XM-U6
PCI-MT64-XM-U6
PCI-MT32-XM-U6
PCI-MT64-XM-U6
PCI-T32-XM-U6
PCI-T64-XM-U6
PCI-T32-XM-U6
PCI-T64-XM-U6
sysMEM
EBRs
OPN
0
0
0
0
0
0
0
(PCI Interface)
External Pins
Resource Utilization
PCI IP Core User’s Guide
48
87
48
87
50
89
50
f
MAX
33
33
66
66
33
33
66