PCI-MT32-XP-N1 Lattice, PCI-MT32-XP-N1 Datasheet - Page 155

• Manufacturer Part Number: PCI-MT32-XP-N1
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-XP-N1

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
LatticeECP2M FPGAs
Table A-5. Performance and Resource Utilization
Ordering Part Number
Table A-6
LatticeECP2M.
Table A-6. OPN for LatticeECP2M PCI IP Core
Target 33 MHz, 32-bit PCI/
Local/Address bus width
Target 33 MHz, 64-bit PCI/
Local/Address bus width
Target 66 MHz, 32-bit PCI/
Local/Address bus width
Target 66 MHz, 64-bit PCI/
Local/Address bus width
Master/Target 33 MHz, 32-bit PCI/
Local/Address bus width
Master/Target 33 MHz, 64-bit PCI/
Local/Address bus width
Master/Target 66 MHz, 32-bit PCI/
Local/Address bus width
Master/Target 66 MHz, 64-bit PCI/
Local/Address bus width
1. Performance and utilization data are generated using an LFE2M-35E-6F672C device with Lattice Diamond 1.0 software. Performance may
vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M family.
User-Configurable Mode
lists the Ordering Part Number (OPNs) for each mode of operation supported by the PCI IP core for
IPexpress
33 MHz
33 MHz
66 MHz
66 MHz
33 MHz
33 MHz
66 MHz
66 MHz
Speed
PCI Bus
SLICEs
32-bit
64-bit
32-bit
64-bit
32-bit
64-bit
32-bit
64-bit
1168
1086
1598
593
722
606
832
856
Master/Target
Master/Target
Master/Target
Master/Target
1
LUTs
1350
1068
1561
1700
2580
717
927
972
Target
Target
Target
Target
155
Type
Registers
472
594
493
614
642
849
663
869
PCI-MT32-PM-U6
PCI-MT64-PM-U6
PCI-MT32-PM-U6
PCI-MT64-PM-U6
PCI-T32-PM-U6
PCI-T64-PM-U6
PCI-T32-PM-U6
PCI-T64-PM-U6
sysMEM
OPN
EBRs
0
0
0
0
0
0
0
0
(PCI Interface)
External Pins
Resource Utilization
PCI IP Core User’s Guide
48
87
48
87
50
89
50
89
f
MAX
33
33
66
66
33
33
66
66