MAX9263GCB/V+T Maxim Integrated, MAX9263GCB/V+T Datasheet
MAX9263GCB/V+T
Related parts for MAX9263GCB/V+T
MAX9263GCB/V+T Summary of contents
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... S of the Serial Link Fault Detection of Serial Link Shorted Together Ground, to Battery, or Open ISO 10605 and IEC 61000-4-2 ESD Tolerance S Applications PART MAX9263GCB/V+ MAX9263GCB/V+T MAX9264GCB/V+ MAX9264GCB/V+T /V denotes an automotive qualified product. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad Tape and reel. Features 2 2 ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer ABSOLUTE MAXIMUM RATINGS AVDD to AGND MAX9263 ............................................................-0.5V to +1.9V MAX9264 ............................................................-0.5V to +3.9V DVDD to GND (MAX9263) ...................................-0.5V to +1.9V DVDD to DGND (MAX9264) .................................-0.5V to +3.9V IOVDD to GND (MAX9263) ..................................-0.5V to ...
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MAX9263 DC ELECTRICAL CHARACTERISTICS (continued 1.7V to 1.9V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL Input Current Low-Level Output Voltage DIFFERENTIAL OUTPUT (OUT+, OUT-) Differential Output ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9263 DC ELECTRICAL CHARACTERISTICS (continued 1.7V to 1.9V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL ESD PROTECTION OUT+, OUT- All Other Pins ...
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MAX9263 AC ELECTRICAL CHARACTERISTICS ( 1.7V to 1.9V, V DVDD AVDD IOVDD Typical values are DVDD AVDD PARAMETER SYMBOL Deterministic Serial Output Jitter t Parallel Data Input Setup Time Parallel Data ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9264 DC ELECTRICAL CHARACTERISTICS (continued 3.0V to 3.6V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL OUTPUT Short-Circuit Current I 2 C/UART, I/O, ...
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MAX9264 DC ELECTRICAL CHARACTERISTICS (continued 3.0V to 3.6V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL POWER SUPPLY Worst-Case Supply Current (Figure 15, Note 3) Sleep Mode ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9264 AC ELECTRICAL CHARACTERISTICS ( 3.0V to 3.6V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL PARALLEL CLOCK OUTPUT (PCLKOUT) Clock Frequency f PCLKOUT ...
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MAX9264 AC ELECTRICAL CHARACTERISTICS (continued 3.0V to 3.6V, V AVDD DVDD IOVDD Typical values are AVDD DVDD PARAMETER SYMBOL Lock Time Power-Up Time OUTPUT TIMING (NOTE 6) ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer ( 1.8V (MAX9263), V AVDD DVDD IOVDD MAX9263 SUPPLY CURRENT vs. PCLK FREQUENCY (24-BIT MODE) 160 PRBS ON, HDCP ON 150 PREEMPHASIS = 0x0B TO 0x0F 140 130 120 ...
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1.8V (MAX9263), V AVDD DVDD IOVDD OUTPUT POWER SPECTRUM vs. PCLK FREQUENCY (VARIOUS MAX9263 SPREAD) 0 -10 0% SPREAD -20 -30 -40 -50 -60 -70 -80 2% SPREAD 4% SPREAD - ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer TOP VIEW DIN0 49 GND 50 IOVDD 51 DIN1 52 DIN2 53 DIN3 54 DIN4 55 DIN5 56 DIN6 57 DIN7 58 DIN8 59 DIN9 60 GND 61 DVDD 62 DIN10 63 DIN11 64 ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer TOP VIEW DOUT8 49 IOGND 50 IOVDD 51 DOUT7 52 DOUT6 53 DOUT5 54 DOUT4 55 DOUT3 56 MAX9264 DOUT2 57 DOUT1 58 DOUT0 59 ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer PIN NAME Data Input [12:16]. Parallel data inputs with internal pulldown to GND. Encrypted when HDCP 1–5 DIN[12:16] is enabled (see Table 3). 6 PCLKIN Parallel Clock Input. Latches parallel data inputs and provides ...
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HDCP Gigabit Multimedia Serial PIN NAME 34 PWDN Active-Low, Power-Down Input. PWDN requires external pulldown or pullup resistor. Receive/Serial Data. UART receive or I IOVDD. In UART mode, RX/SDA is the Rx input of the serializer’s UART ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer PIN NAME Active-Low Parallel Output-Enable Input. Requires an external pulldown or pullup resistor. Set 1 ENABLE = low to enable PCLKOUT, SD, SCK, WS, and DOUT_. Set ENABLE = high to put ENABLE PCLKOUT, ...
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PIN NAME 19 PWDN Active-Low, Power-Down Input. PWDN requires an external pulldown or pullup resistor. Active-Low Open-Drain Video Data Error Output with Internal 60kI Pullup to IOVDD. ERR goes low when the number of decoding errors during normal operation exceed ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer PIN NAME Data Output [7:0]. Parallel data outputs. Output data can be strobed on the selected edge of 52–59 DOUT[7:0] PCLKOUT. Encrypted when HDCP is enabled. See Table 3. Spread-Spectrum Enable Input. Serial link ...
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HDCP Gigabit Multimedia Serial PCLKOUT SSPLL RGB[17:0] RGB DOUT[17:0] HS DOUT18/ DOUT19/VS VIDEO DE DE DOUT20 RGB[23:18] DOUT[26:21] (4-CH) (4-CH) DOUT27 FIFO (4-CH) DIN[28:27] (4-CH) DOUT28/MCLK (4-CH) ACB AUDIO FCC SD SCK WS Link Serializer/Deserializer Functional Diagrams ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer OUT- V OS(-) OUT+ V OD(-) (OUT+) - (OUT-) Figure 1. Serializer Serial-Output Parameters OUT OUT- Figure 2. Serializer Output Waveforms at OUT+, OUT OUT OUT- ...
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OUTPUT LOGIC (OUT+) LFLT OUTPUT LOGIC (OUT-) Figure 3. Line-Fault Detector Circuit NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE. Figure 4. Serializer Worst-Case Pattern Input HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MAX9263 45kI* LMN0 LMN1 5kI* OUT+ OUT- REFERENCE VOLTAGE ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer PCLKIN t F Figure 5. Serializer Parallel Input Clock Requirements t R TX/ SCL RX/ SDA Figure Timing Parameters 800mV P-P Figure 7. Serializer Differential Output Template 22 ...
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PCLKIN DIN_ Figure 8. Serializer Input Setup and Hold Times DIN_ N N+1 PCLKIN OUT+/- Figure 9. Serializer Delay HDCP Gigabit Multimedia Serial Link Serializer/Deserializer V IH MIN V IL MAX t SET V IH MIN V IL MAX NOTE: ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer PCLKIN REVERSE CONTROL CHANNEL Figure 10. Serializer Link Startup Time PCLKIN PWDN POWERED DOWN REVERSE CONTROL CHANNEL DISABLED Figure 11. Serializer Power-Up Delay 24 t LOCK 350Fs SERIAL LINK INACTIVE SERIAL LINK ACTIVE CHANNEL ...
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WS SCK SD 2 Figure 12. Input I S Timing Parameters IN+ V CMR IN- V ROH 0 ROH 0 ROH (IN+) - (IN Figure 13. Reverse Control-Channel Output Parameters HDCP Gigabit Multimedia Serial ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer IN IN- _ Figure 14. Test Circuit for Differential Input Measurement PCLKOUT Figure 16. Deserializer Clock Output High and Low Times ...
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SERIAL-WORD LENGTH SERIAL WORD N IN+/- FIRST BIT LAST BIT DOUT_ PARALLEL WORD N-2 PCLKOUT NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE. Figure 18. Deserializer Delay IN+ - IN- t LOCK LOCK PWDN MUST BE HIGH Figure 19. Deserializer Lock ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Detailed Description The MAX9263/MAX9264 serializer/deserializer chipset utilizes Maxim’s GMSL technology and HDCP. When HDCP is enabled, the serializer/deserializer encrypt video and audio data on the serial link. The serializer/ deserializer are backward compatible with ...
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Table 1. Power-Up Default Register Map (see Tables 22 and 24) (continued) REGISTER POWER-UP DEFAULT ADDRESS (hex) (hex) 0x05 0x70 0x06 0x40 0x07 0x22 0x0A 0x08 (read only) 0x0C 0x70 0x0D 0x0F 0x05 0x1E (read only) 0x1X 0x1F (read only) ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 1. Power-Up Default Register Map (see Tables 22 and 24) (continued) REGISTER POWER-UP DEFAULT ADDRESS (hex) (hex) 0x98 to 0x9C 0x0000000000 0x9D to 0x9F 0x000000 0xA0 to 0xA3 0x00000000 0xA4 to 0xA7 0x00000000 ...
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Table 2. Power-Up Default Register Map (see Tables 23 and 25) (continued) REGISTER POWER-UP DEFAULT ADDRESS (hex) (hex) 0x05 0x24 or 0x29 0x06 0x0F 0x07 0x54 0x08 0x30 0x09 0xC8 0x0A 0x12 0x0B 0x20 0x0C 0x00 0x00 0x0D (read only) ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 2. Power-Up Default Register Map (see Tables 23 and 25) (continued) REGISTER POWER-UP DEFAULT ADDRESS (hex) (hex) 0xXX 0x87 (read only) 0x00000000 0x88 to 0x8F 00000000 0x00000000 0x90 to 0x94 00000000 0x95 0x00 ...
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HDCP Bitmapping and Bus-Width Selection The parallel input/outputs have two selectable modes, 24-bit mode and 32-bit mode. In 24-bit mode, DIN[28:21] are not available. For both modes, the SD, SCK, and WS 2 pins are for I S audio. The ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer DIN0 DIN1 DIN17 RGB DATA NOTE: LOCATIONS OF THE RGB DATA ARE INTERCHANGABLE ACCORDINGLY ON BOTH SIDES OF THE LINK. ONLY DIN[17:0], DIN[26:21] AND ACB HAVE HDCP ENCRYPTION. Figure 23. 32-Bit ...
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PCLKIN frequencies. Spread-spectrum settings do not affect 2 the I S data rate or WS clock frequency. Additional MCLK Output for Audio Applications Some audio DACs, such as the MAX9850, do not require ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer 1Mbps in both directions. The serializer and deserial- izer automatically detect the control-channel bit rate in base mode. Packet bit rates can vary up to 3.5x from the previous bit rate. See the Changing ...
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UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 0) SERIALIZER/DESERIALIZER SYNC FRAME DEVICE REGISTER ADDRESS SERIALIZER/DESERIALIZER PERIPHERAL UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 0) SERIALIZER/DESERIALIZER ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer 2 UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 1) SERIALIZER/DESERIALIZER SYNC FRAME DEVICE REGISTER ADDRESS SERIALIZER/DESERIALIZER PERIPHERAL UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD ...
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Table 6. Serializer CML Driver Strength (Default Level, CMLLVL = 11) PREEMPHASIS SETTING PREEMPHASIS LEVEL (dB)* -6.0 -4.1 -2.5 -1.2 0 1.1 2.2 3.3 4.4 6.0 8.0 10.5 14.0 *Negative preemphasis levels denote deemphasis. Table 7. Deserializer Cable Equalizer Boost ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Spread Spectrum To reduce the EMI generated by the transitions on the serial link and parallel outputs, both the serial- izer and deserializer support spread spectrum. Turning on spread spectrum on the deserializer spreads ...
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Manual Programming of the Spread-Spectrum Divider The modulation rate for the serializer/deserializer relates to the PCLK_ frequency as follows: f PCLK_ = + f (1 DRS) M MOD SDIV × where Modulation frequency M DRS = DRS pin ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer outputs of the device remain high impedance. Entering power-down mode resets the internal registers of the device. In addition, upon exiting power-down mode, the serializer/deserializer relatch the state of external pins SSEN, DRS, AUTOS, ...
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Case 3: Remote Side Autostart Mode After power-up or when PWDN transitions from low to high, the remote device (deserializer) starts up and tries to lock to an incoming serial signal with sufficient power. The host side (serializer ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer MS PIN SLEEP BIT SETTING POWER-UP VALUE SLEEP LOW 0 HIGH 1 SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES AFTER FC SETS SLEEP = 1 INT CHANGES FROM LOW TO HIGH OR SEND INT ...
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POWER-UP VALUE AUTOS PIN SETTING SEREN SLEEP LOW 1 HIGH 0 SLEEP = 1 FOR > 8ms SLEEP REVERSE LINK WAKE-UP SIGNAL PWDN = HIGH, POWER-ON, SLEEP = 1 AUTOS = HIGH POWER-DOWN PWDN = LOW OR ALL STATES OR ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer then reads the deserializer KSV (BKSV) and writes it to the serializer. The FC begins checking BKSV against the revocation list. Using the cipher, the serializer and dese- rializer calculate a 16-bit response value, ...
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Force Video/Force Audio Data The serializer masks audio and video data through two control bits: FORCE_AUDIO and FORCE_VIDEO. Set FORCE_VIDEO = 1 to transmit the 24-bit data word in the DFORCE register instead of the video data received at the ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 15. Startup, HDCP Authentication, and Normal Operation (Deserializer is not a Repeater)—First Part of the HDCP Authentication Protocol (continued) NO. µC Reads the BKSV and REPEATER bit from the deserializer 8 and writes ...
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Table 16. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption is Enabled (continued) NO. µ does not match RI’, link integrity check fails. After the detection of failure of link integrity check, the FC ensures that A/V ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Example Repeater Network—Two µCs The following example has one repeater and two FCs (Figure 34). Table 18 summarizes the authentication operation. BD-DRIVE TX_B1 µC_B MEMORY WITH SRM Figure 34. Example Network with One Repeater ...
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Table 18. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First and Second Parts of the HDCP Authentication Protocol (continued) NO. µC_B Makes sure that the A/V data not requiring protection (low-value content) is available at the TX_B1 inputs (such ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 18. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First and Second Parts of the HDCP Authentication Protocol (continued) NO. µC_B Waits for the VSYNC falling edge and then enables encryption on the ...
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Table 18. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First and Second Parts of the HDCP Authentication Protocol (continued) NO. µC_B Reads the KSV list and BINFO from RX_R1 and writes them to TX_B1. If any of the MAX_DEVS_EXCEEDED ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Applications Information The deserializer checks the serial link for errors and stores the number of detected decoding errors in the 8-bit register DECERR (0x0D large number of 8b/10b decoding or parity errors ...
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Jitter-Filtering PLL In some applications, the parallel bus input clock to the serializer (PCLKIN) includes noise, which reduces link reliability. The serializer has a narrowband jitter-filtering PLL to attenuate frequency components outside the PLL’s bandwidth (< 100kHz typ). Enable the ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer required external resistor connections. LFLT = low when a line fault is detected and LFLT goes high when the line returns to normal. The line-fault type is stored in 0x08, D[3:0] of the serializer. ...
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AC-coupling isolates the receiver from DC voltages up to the voltage rating of the capacitor. Four capacitors—two at the serializer output and two at the deserializer input— are needed for proper link operation and to provide protection if either end ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer R D 330I CHARGE-CURRENT- DISCHARGE LIMIT RESISTOR RESISTANCE HIGH- C STORAGE VOLTAGE S 150pF CAPACITOR DC SOURCE Figure 36. IEC 61000-4-2 Contact Discharge ESD Test Circuit Table 22. Serializer GMSL Core Register Table (See ...
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Table 22. Serializer GMSL Core Register Table (See Table 1) (continued) REGISTER BITS NAME ADDRESS D[7:6] AUTOFM 0x03 D[5:0] SDIV D7 SEREN D6 CLINKEN D5 PRBSEN 0x04 D4 SLEEP D[3:2] INTTYPE D1 REVCCEN D0 FWDCCEN HDCP Gigabit Multimedia Serial Link ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 22. Serializer GMSL Core Register Table (See Table 1) (continued) REGISTER BITS NAME ADDRESS D7 I2CMETHOD D6 DISFPLL D[5:4] CMLLVL 0x05 D[3:0] PREEMP 0x06 D[7:0] — 0x07 D[7:0] — D[7:4] — D[3:2] LFNEG ...
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Table 22. Serializer GMSL Core Register Table (See Table 1) (continued) REGISTER BITS NAME ADDRESS D7 SETINT D6 INVVSYNC 0x0D D5 INVHSYNC D[4:0] — 0x1E D[7:0] ID D[7:5] — 0x1F D4 CAPS D[3:0] REVISION Table 23. Deserializer GMSL Core Register ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 23. Deserializer GMSL Core Register Table (See Table 2) (continued) REGISTER BITS NAME ADDRESS D[7:6] AUTOFM 0x03 D5 — D[4:0] SDIV D7 LOCKED D6 OUTENB D5 PRBSEN D4 SLEEP 0x04 D[3:2] INTTYPE D1 ...
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Table 23. Deserializer GMSL Core Register Table (See Table 2) (continued) REGISTER BITS NAME ADDRESS D7 I2CMETHOD D[6:5] HPFTUNE D4 PDHF 0x05 D[3:0] EQTUNE D7 DISSTAG D7 — D6 AUTORST D5 DISINT 0x06 D4 INT D3 GPIO1OUT D2 GPIO1 D1 ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 23. Deserializer GMSL Core Register Table (See Table 2) (continued) REGISTER BITS NAME ADDRESS 0x07 D[7:0] — D[7:2] — D1 DISVSFILT 0x08 D0 DISHSFILT 0x09 D[7:0] — 0x0A D[7:0] — 0x0B D[7:0] — ...
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Table 24. Serializer HDCP Register Table (See Table 1) REGISTER SIZE NAME ADDRESS (Bytes) 0x80 to 0x84 5 BKSV 0x85 to 0x86 2 RI/RI’ 0x87 1 PJ/PJ’ 0x88 to 0x8F 8 AN 0x90 to 0x94 5 AKSV 0x95 1 ACTRL ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 24. Serializer HDCP Register Table (See Table 1) (continued) REGISTER SIZE NAME ADDRESS (Bytes) 0x96 1 ASTATUS 0x97 1 BCAPS 0x98 to 0x9C 5 ASEED 0x9D to 0x9F 3 DFORCE V.H0, 0xA0 to ...
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Table 24. Serializer HDCP Register Table (See Table 1) (continued) REGISTER SIZE NAME ADDRESS (Bytes) V.H4, 0xB0 to 0xB3 4 V’.H4 0xB4 to 0xB5 2 BINFO 0xB6 1 GPMEM 0xB7 to 0xB9 3 — 0xBA to 0xFF 70 KSV_LIST HDCP ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer Table 25. Deserializer HDCP Register Table (See Table 2) REGISTER SIZE NAME ADDRESS (Bytes) 0x80 to 0x84 5 BKSV 0x85 to 0x86 2 RI’ 0x87 1 PJ’ 0x88 to 0x8F 8 AN 0x90 to ...
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Table 25. Deserializer HDCP Register Table (See Table 2) (continued) REGISTER SIZE NAME ADDRESS (Bytes) 0xB4 to 0xB5 2 BINFO 0xB6 1 GPMEM 0xB7 to 0xB9 3 — 0xBA to 0xFF 70 KSV_LIST HDCP Gigabit Multimedia Serial Link Serializer/Deserializer READ/ ...
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HDCP Gigabit Multimedia Serial Link Serializer/Deserializer PCLKIN PCLK DIN[17:0] RGB DIN18/HS HS DIN19/VS VS DIN20 DE GPU CDS AUTOS ECU MAX9263 TX RX/SDA UART TX/SCL RX LFLT LFLT INT INT SCK SCK AUDIO SD SD NOTE: ...
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... Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © ...