MAX9263GCB/V+T Maxim Integrated, MAX9263GCB/V+T Datasheet - Page 55

• Manufacturer Part Number: MAX9263GCB/V+T
• Description: Serializers & Deserializers - Serdes GMSL Serializer w/HDCP Interface
• Manufacturer: Maxim Integrated

In some applications, the parallel bus input clock to the
serializer (PCLKIN) includes noise, which reduces link
reliability. The serializer has a narrowband jitter-filtering
PLL to attenuate frequency components outside the
PLL’s bandwidth (< 100kHz typ). Enable the jitter-filtering
PLL by setting DISFPLL = 0 (0x05, D6).
Both the video clock rate (f
channel clock rate (f
to support applications with multiple clock speeds. It is
recommended to enable the serial link after the video
clock stabilizes. Stop the video clock for 5Fs and restart
the serial link or toggle SEREN after each change in
the video clock frequency to recalibrate any automatic
settings if a clean frequency change cannot be guaran-
teed. The reverse control channel remains unavailable
for 350Fs after serial link start or stop. Limit on-the-fly
changes in f
ensure that the device recognizes the UART sync pat-
tern. For example, when lowering the UART frequency
from 1Mbps to 100kbps, first send data at 333kbps and
then at 100kbps to have reduction ratios of 3 and 3.333,
respectively.
Do not interrupt PCLKIN or change its frequency while
encryption is enabled. Otherwise HDCP synchronization
is lost and authentication must be repeated. To change
the PCLK frequency, stop the high value content A/V
data. Then disable encryption in the serializer/deserial-
izer within the same VSYNC cycle—encryption stops
at the next VSYNC falling edge. PCLKIN can now be
changed/stopped. Reenable encryption before sending
any high value content A/V data.
A measure of link quality is the recovery time from loss
of HDCP synchronization. With the GMSL, it is likely that
HDCP synchronization will not be lost unless the GMSL
synchronization is lost. The host can be quickly notified
of loss-of-lock by connecting the deserializer’s LOCK
output to the INT input. If other sources use the interrupt
input, such as a touch-screen controller, the FC can
implement a routine to distinguish between interrupts
from loss-of-sync and normal interrupts. Reverse con-
trol-channel communication does not require an active
forward link to operate and accurately tracks the LOCK
status of the GMSL link. LOCK asserts for video link only
and not for the configuration link.
Fast Detection of Loss-of-Synchronization
UART
Changing the Clock Frequency
to factors of less than 3.5 at a time to
UART
) can be changed on-the-fly
PCLK_
Jitter-Filtering PLL
) and the control-
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
Both the serializer and the deserializer have programma-
ble device addresses. This allows multiple GMSL devic-
es, along with I
control channel. The serializer device address is stored
in register 0x00 of each device, while the deserializer
device address is stored in register 0x01 of each device.
To change the device address, first write to the device
whose address changes (register 0x00 of the serializer
for serializer device address change, or register 0x01 of
the deserializer for deserializer device address change).
Then write the same address into the corresponding reg-
ister on the other device (register 0x00 of the deserializer
for serializer device address change, or register 0x01 of
the serializer for deserializer device address change).
The serializer/deserializer can block changes to their
non-HDCP registers. Set CFGBLOCK to make all non-
HDCP registers as read only. Once set, the registers
remain blocked until the supplies are removed or until
PWDN is low.
The serializer and deserializer are backward compatible
with the non-HDCP MAX9259 and MAX9260. The pin-
outs and packages are the same for both devices. See
Table 3 and the Pin Description section for backward-
compatible pin mapping.
Each device has a unique HDCP key set that is stored
in secure on-chip nonvolatile memory (NVM). The HDCP
key set consists of forty 56-bit private keys and one
40-bit public key. The NVM is qualified for automotive
applications.
The deserializer has two open-drain GPIOs available.
When not used for HDCP purposes, GPIO1OUT and
GPIO0OUT (0x06, D3 and D1) set the output state of the
GPIOs. See the Notification of Start of Authentication and
Enable of Encryption to Downstream Links section. The
GPIO input buffers are always enabled. The input states
are stored in GPIO1 and GPIO0 (0x06, D2 and D0). Set
GPIO1OUT/GPIO0OUT to 1 when using GPIO1/GPIO0
as an input.
The line-fault detector in the serializer monitors for line
failures such as short to ground, short to battery, and
open link for system fault diagnosis. Figure 3 shows the
Programming the Device Addresses
2
C peripherals, to coexist on the same
Backward Compatibility
Configuration Blocking
Line-Fault Detection
Key Memory
GPIOs
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