MAX9263GCB/V+T Maxim Integrated, MAX9263GCB/V+T Datasheet - Page 41

• Manufacturer Part Number: MAX9263GCB/V+T
• Description: Serializers & Deserializers - Serdes GMSL Serializer w/HDCP Interface
• Manufacturer: Maxim Integrated

Table 11. Serializer Modulation Coefficients and Maximum SDIV Settings
Table 12. Deserializer Modulation Coefficients and Maximum SDIV Settings
The modulation rate for the serializer/deserializer relates
to the PCLK_ frequency as follows:
where:
f
DRS = DRS pin input value (0 or 1)
f
MOD = Modulation coefficient given in Table 11 or 12
SDIV = 6- or 5-bit SDIV setting, manually programmed
by the FC
To program the SDIV setting, first look up the modulation
coefficient according to the part number and desired
bus-width and spread-spectrum settings. Solve the
above equation for SDIV using the desired pixel clock
and modulation frequencies. If the calculated SDIV
value is larger than the maximum allowed SDIV value in
Table 11 or 12, set SDIV to the maximum value.
M
PCLK_
= Modulation frequency
SPREAD-SPECTRUM SETTING (%)
BIT-WIDTH MODE
= PCLK_ frequency
32 bit
24 bit
f
M
=
4
2
(1 DRS)
Manual Programming of the
+
Spread-Spectrum Divider
MOD SDIV
f
PCLK_
×
SPREAD-SPECTRUM
SETTING (%)
HDCP Gigabit Multimedia Serial
MODULATION COEFFICIENT (dec)
0.5
1.5
0.5
1.5
1
3
4
2
1
3
4
2
Link Serializer/Deserializer
208
208
The serializer/deserializer include a low-power sleep
mode to reduce power consumption on the device not
attached to the FC (the deserializer in LCD applications
and the serializer in camera applications). Set the cor-
responding remote IC’s SLEEP bit to 1 to initiate sleep
mode. The serializer sleeps immediately after setting
its SLEEP = 1. The deserializer sleeps after serial link
inactivity or 8ms (whichever arrives first) after setting
its SLEEP = 1. See the Link Startup Procedure section
for details on waking up the device for different FC and
starting conditions.
The FC side device cannot enter into sleep mode. If
an attempt is made to program the FC side device for
sleep, the SLEEP bit remains 0. Use the PWDN input
pin to bring the FC side device into a low-power state.
Entering sleep mode resets the HDCP registers, but not
the configuration registers.
The serializer/deserializer include a power-down mode
to further reduce power consumption. Set PWDN low to
enter power-down mode. While in power-down mode, the
COEFFICIENT MOD (dec)
MODULATION
104
104
152
152
204
204
112
112
152
152
80
80
SDIV UPPER LIMIT (dec)
SDIV UPPER LIMIT (dec)
Power-Down Mode
15
30
40
63
27
54
15
30
52
63
37
63
21
42
Sleep Mode
41