MAX9263GCB/V+T Maxim Integrated, MAX9263GCB/V+T Datasheet - Page 36

• Manufacturer Part Number: MAX9263GCB/V+T
• Description: Serializers & Deserializers - Serdes GMSL Serializer w/HDCP Interface
• Manufacturer: Maxim Integrated

36
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
Figure 24. GMSL UART Protocol for Base Mode
Figure 25. GMSL UART Data Format for Base Mode
1Mbps in both directions. The serializer and deserial-
izer automatically detect the control-channel bit rate in
base mode. Packet bit rates can vary up to 3.5x from the
previous bit rate. See the Changing the Clock Frequency
section.
Figure 24 shows the UART protocol for writing and read-
ing in base mode between the µC and the serializer/
deserializer.
Figure 25 shows the UART data format. Figures 26 and
27 detail the formats of the SYNC byte (0x79) and the
ACK byte (0xC3). The FC and the connected slave chip
Figure 26. SYNC Byte (0x79)
START
D0
1
D1
0
START
D2
0
SYNC
SYNC
D3
1
D0
FRAME 1
DEV ADDR + R/W
DEV ADDR + R/W
D4
1
D5
1
D1
MASTER WRITES TO SLAVE
D6
1
STOP
REG ADDR
REG ADDR
D2
D7
0
PARITY STOP
START
MASTER WRITES TO SLAVE
D3
NUMBER OF BYTES
NUMBER OF BYTES
READ DATA FORMAT
1 UART FRAME
WRITE DATA FORMAT
D4
FRAME 2
Figure 27. ACK Byte (0xC3)
generate the SYNC byte and ACK byte, respectively.
Events such as device wake-up and interrupt generate
transitions on the control channel that should be ignored
by the FC. Data written to the serializer/deserializer
registers do not take effect until after the acknowledge
byte is sent. This allows the FC to verify write commands
received without error, even if the result of the write
command directly affects the serial link. The slave uses
the SYNC byte to synchronize with the host UART data
rate automatically. If the INT or MS inputs of the deserial-
izer toggle while there is control-channel communication,
the control-channel communication can be corrupted.
MASTER READS FROM SLAVE
START
D5
BYTE 1
ACK
D0
1
D6
D1
1
STOP
BYTE 1
D2
0
BYTE N
D7
START
MASTER READS FROM SLAVE
D3
0
PARITY
D4
0
BYTE N
D5
0
ACK
FRAME 3
STOP
D6
1
D7
1
PARITY STOP