MAX9263GCB/V+T Maxim Integrated, MAX9263GCB/V+T Datasheet - Page 34

• Manufacturer Part Number: MAX9263GCB/V+T
• Description: Serializers & Deserializers - Serdes GMSL Serializer w/HDCP Interface
• Manufacturer: Maxim Integrated

34
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
Figure 23. 32-Bit Mode Serial Link Data Format
Table 4. Maximum Audio WS Frequency (kHz) for Various PCLKIN Frequencies
bit carries the forward control data. The last bit (PCB) is
the parity bit of the previous 23 or 31 bits.
The serializer uses the reverse control channel to receive
I
the opposite direction of the video stream. The reverse
control channel and forward video data coexist on
the same twisted pair forming a bidirectional link. The
reverse control channel operates independently from the
forward control channel. The reverse control channel is
available 500Fs after power-up. The serializer temporar-
ily disables the reverse control channel for 350Fs after
starting/stopping the forward serial link.
The serializer/deserializer use the DRS input to set the
PCLKIN frequency range. Set DRS high for a PCLKIN
frequency range of 6.25MHz to 12.5MHz (32-bit mode)
or 8.33MHz to 16.66MHz (24-bit mode). Set DRS low
for normal operation with a PCLKIN frequency range
2
C/UART and interrupt signals from the deserializer in
LENGTH
WORD
(bits)
16
18
20
24
32
8
NOTE: LOCATIONS OF THE RGB DATA ARE INTERCHANGABLE
DIN0
R0
ACCORDINGLY ON BOTH SIDES OF THE LINK.
ONLY DIN[17:0], DIN[26:21] AND ACB HAVE HDCP ENCRYPTION.
DIN1
R1
RGB DATA
> 192
> 192
185.5
174.6
152.2
123.7
12.5
Reverse Control Channel
DIN17
PCLKIN FREQUENCY
Data-Rate Selection
B5
(DRS = LOW) (MHz)
> 192
> 192
> 192
> 192
182.7
148.4
15
DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 DIN24 DIN25 DIN26 DIN27 DIN28
HS
CONTROL BITS
VS
> 192
> 192
> 192
> 192
> 192
164.3
16.6
DE
R6
32 BITS
> 192
> 192
> 192
> 192
> 192
> 192
R7
> 20
of 12.5MHz to 78MHz (32-bit mode) or 16.66MHz to
104MHz (24-bit mode).
The I
from 8kHz to 192kHz and audio word lengths from 4 bits
to 32 bits. The audio bit clock (SCK) does not have to be
synchronized with PCLKIN. The serializer automatically
encodes audio data into a single bit stream synchronous
with PCLKIN. The deserializer decodes the audio stream
and stores audio words in a FIFO. Audio rate detection
uses an internal oscillator to continuously determine the
audio data rate and output the audio in I
audio channel is enabled by default. When the audio
channel is disabled, the audio data on the serializer and
deserializer are treated as an additional parallel signal
(DIN_/DOUT_).
Since the audio data sent through the serial link is
synchronized with PCLKIN, low PCLKIN frequencies
limit the maximum audio sampling rate. Table 4 lists
G6
RGB DATA
2
S audio channel supports audio sampling rates
G7
> 192
> 192
185.5
174.6
152.2
123.7
6.25
B6
B7
PCLKIN FREQUENCY
(DRS = HIGH) (MHz)
CONTROL BITS
> 192
> 192
> 192
> 192
182.7
148.4
VIDEO DATA/
ADDITIONAL
7.5
CHANNEL
AUDIO
ACB
BIT
> 192
> 192
> 192
> 192
> 192
164.3
8.33
CHANNEL BIT
CONTROL-
FORWARD
Audio Channel
FCC
CHECK BIT
2
PACKET
PARITY
S format. The
PCB
> 192
> 192
> 192
> 192
> 192
> 192
> 10