MAX9263GCB/V+T Maxim Integrated, MAX9263GCB/V+T Datasheet - Page 52

• Manufacturer Part Number: MAX9263GCB/V+T
• Description: Serializers & Deserializers - Serdes GMSL Serializer w/HDCP Interface
• Manufacturer: Maxim Integrated

52
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
Table 18. HDCP Authenticaion and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
NO.
10
11
12
13
9
Waits for the VSYNC falling edge
and then enables encryption on the
(TX_B1, RX_R1) link. Full
authentication is not yet complete,
so it ensures that A/V content that
needs protection is not transmitted.
Since REPEATER = 1 was read
from RX_R1, the second part of
authentication is required.
—
Waits for some time to allow FC_R
to make the KSV list ready in
RX_R1. Then polls (reads) the
KSV_LIST_READY bit of RX_R1
regularly until the proper acknowl-
edge frame is received and the bit
is read as 1.
µC_B
—
When GPIO_0 = 1 is detected,
enables encryption on the (TX_R1,
RX_D1) and (TX_R2, RX_D2) links.
Blocks the control channel from the
FC_B side by setting REVCCEN =
FWDCCEN = 0 in RX_R1. Retries
until the proper acknowledge frame
is received.
Writes BKSVs of RX_D1 and RX_D2
to the KSV list in RX_R1. Then cal-
culates and writes the BINFO regis-
ter of RX_R1.
Writes 1 to the KSV_LIST_READY
bit of RX_R1 and then unblocks the
control channel from the FC_B side
by setting REVCCEN = FWDCCEN
= 1 in RX_R1.
µC_R
TX_B1: Encryption
is enabled after the
next VSYNC falling
edge.
TX_R1, TX_R2:
Encryption is
enabled after the
next VSYNC falling
edge.
—
—
—
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
(TX_B1, TX_R1,
SERIALIZER
TX_R2)
RX_R1: Decryption
is enabled after the
next VSYNC falling
edge.
RX_D1, RX_D2:
Decryption is
enabled after the
next VSYNC falling
edge.
RX_R1: Control
channel from the
serializer side
(TX_B1) is blocked
after FWDCCEN =
REVCCEN = 0 is
written.
RX_R1: Triggered
by FC_R’s write of
BINFO, calculates
the hash-value,
V’, on the KSV list,
BINFO, and the
secret-value M0’.
RX_R1: Control
channel from the
serializer side (TX_
B1) is unblocked
after FWDCCEN =
REVCCEN = 1 is
written.
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)