MAX9263GCB/V+T Maxim Integrated, MAX9263GCB/V+T Datasheet - Page 16

• Manufacturer Part Number: MAX9263GCB/V+T
• Description: Serializers & Deserializers - Serdes GMSL Serializer w/HDCP Interface
• Manufacturer: Maxim Integrated

16
HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
10, 64
7, 63
PIN
8, 9
11
12
13
14
15
16
17
18
1
2
3
4
5
6
ENABLE
IN+, IN-
RX/SDA
TX/SCL
GPIO0
GPIO1
NAME
AGND
DGND
AVDD
DVDD
BWS
CDS
EQS
DCS
INT
MS
ES
Active-Low Parallel Output-Enable Input. Requires an external pulldown or pullup resistor. Set
ENABLE = low to enable PCLKOUT, SD, SCK, WS, and DOUT_. Set ENABLE = high to put
PCLKOUT, SD, SCK, WS, and DOUT_ into high impedance.
Bus-Width Select. BWS requires an external pulldown or pullup resistor. Set BWS = low for
24-bit mode. Set BWS = high for 32-bit mode.
Interrupt Input. INT requires an external pullup or pulldown resistor. A transition on the
deserializer’s INT input toggles the serializer’s INT output.
Control Direction Selection. Control link direction selection input requires external pulldown or
pullup resistor. Set CDS = high for UART connection of a FC as control-channel master. Set
CDS = low for peripheral connection as a control-channel I
GPIO0. Open-drain general-purpose input/output with an internal 60kI pullup resistor to
IOVDD. GPIO0 is high impedance during power-up and when PWDN = low.
Edge Select. PCLKOUT edge-selection input requires an external pulldown or pullup resistor.
Set ES = low for a rising-edge trigger. Set ES = high for a falling-edge trigger.
3.3V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller capacitor closest to AVDD.
Differential CML Input Q. Differential inputs of the serial link.
Analog Ground
Equalizer Select Input Requires an External Pulldown or Pullup Resistor. The state of EQS
latches upon power-up or when resuming from power-down mode (PWDN = low). Set EQS =
low for 10.7dB equalizer boost (EQTUNE = 1001). Set EQS = high for 5.2dB equalizer boost
(EQTUNE = 0100).
GPIO1. Open-drain general-purpose input/output with an internal 60kI pullup resistor to
IOVDD. GPIO1 is high impedance during power-up and when PWDN = low.
Drive Current Select. Driver current-selection input requires an external pulldown or
pullup resistor to IOVDD. Set DCS = high for stronger parallel data and clock output drivers.
Set DCS = low for normal parallel data and clock drivers. See the MAX9264 DC Electrical
Characteristics table.
Mode Select. Control-channel mode selection input requires an external pulldown or
pullup resistor. MS sets the control-link mode when CDS = high. See the Control-Channel and
Register Programming section. MS sets autostart mode when CDS = low. See Table 13.
3.3V Digital Power Supply. Bypass DVDD to DGND with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller capacitor closest to DVDD.
Digital Ground
Receive/Serial Data. UART receive or I
IOVDD. In UART mode, RX/SDA is the Rx input of the deserializer’s UART. In I
RX/SDA is the SDA input/output of the deserializer’s I
driver and requires a pullup resistor.
Transmit/Serial Clock. UART transmit or I
IOVDD. In UART mode, TX/SCL is the Tx output of the deserializer’s UART. In I
TX/SCL is the SCL output of the deserializer’s I
requires a pullup resistor.
2
C serial-data input/output with internal 30kI pullup to
2
FUNCTION
C serial-clock output with internal 30kI pullup to
2
C master. TX/SCL is an open-drain driver and
MAX9264 Pin Description
2
C master. RX/SDA has an open-drain
2
C or UART slave.
2
2
C mode,
C mode,