CY7C1021DV33-10BVXI Cypress Semiconductor Corp, CY7C1021DV33-10BVXI Datasheet - Page 5

• Manufacturer Part Number: CY7C1021DV33-10BVXI
• Description: IC SRAM 1MBIT 10NS 48VFBGA
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C1021DV33-10BVXI

• Memory Size: 1M (64K x 16)
• Package / Case: 48-VFBGA
• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 10 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 60 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 64K X 16
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: FBGA
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2006

Document #: 38-05460 Rev. *F
Switching Characteristics
Notes
10. At any given temperature and voltage condition, t
11. This parameter is guaranteed by design and is not tested.
12. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
8. t
9. t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that
terminates the Write.
[11]
[11]
POWER
HZOE
Parameter
[8]
, t
HZBE
gives the minimum amount of time that the power supply should be at typical V
, t
[12]
HZCE
, and t
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low-Z
WE LOW to High-Z
Byte Enable to End of Write
HZWE
CC
(typical) to the first access
are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state
Over the Operating Range
Description
[10]
[10]
[9, 10]
[9, 10]
[10]
[9, 10]
HZCE
is less than t
LZCE
, t
HZOE
[7]
is less than t
-10 (Ind’l/Auto-A)
Min.
100
10
10
3
0
3
0
8
8
0
0
7
5
0
3
0
7
CC
LZOE
values until the first memory access can be performed.
, and t
Max.
HZWE
10
10
10
5
5
5
5
6
5
is less than t
LZWE
Min.
100
12
12
3
0
3
0
0
9
9
0
0
8
6
0
3
8
-12 (Auto-E)
for any given device.
CY7C1021DV33
Max.
12
12
12
6
6
6
6
6
6
Page 5 of 13
Unit
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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