CY7C1350G-133AXC Cypress Semiconductor Corp, CY7C1350G-133AXC Datasheet - Page 10

• Manufacturer Part Number: CY7C1350G-133AXC
• Description: IC SRAM 4.5MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1350G-133AXC

• Memory Size: 4.5M (128K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 4 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 225 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 128K X 36
• Clock Frequency: 133MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Density: 4Mb
• Access Time (max): 4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 225mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2116; CY7C1350G-133AXC

Switching Characteristics
Over the Operating Range
Document Number: 38-05524 Rev. *I
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ALS
WES
CENS
DS
CES
AH
ALH
WEH
CENH
DH
CEH
15. Timing reference level is 1.5 V when V
16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
17. This part has a voltage regulator internally; t
18. t
19. At any given voltage and temperature, t
20. This parameter is sampled and not 100% tested.
Parameter
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve tri-state prior to low Z under the same system conditions.
CHZ
, t
CLZ
,t
OELZ
V
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z
Clock to high Z
OE LOW to output valid
OE LOW to output low Z
OE HIGH to output high Z
Address set-up before CLK rise
ADV/LD set-up before CLK rise
GW, BW
CEN set-up before CLK rise
Data input set-up before CLK rise
Chip enable set-up before CLK rise
Address hold after CLK rise
ADV/LD hold after CLK rise
GW, BW
CEN hold after CLK rise
Data input hold after CLK rise
Chip enable hold after CLK rise
, and t
DD
(typical) to the first access
OEHZ
X
X
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
set-up before CLK rise
hold after CLK rise
Description
[15, 16]
[18, 19, 20]
[18, 19, 20]
DDQ
OEHZ
POWER
= 3.3 V and is 1.25 V when V
is less than t
[18, 19, 20]
[18, 19, 20]
is the time that the power needs to be supplied above V
[17]
OELZ
Min
4.0
1.7
1.7
1.0
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
and t
1
–
0
–
–
0
–
–250
CHZ
Max
2.6
2.6
2.6
2.6
is less than t
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DDQ
= 2.5 V.
Min
5.0
2.0
2.0
1.0
1.2
1.2
1.2
1.2
1.2
1.2
0.5
0.5
0.5
0.5
0.5
0.5
1
–
0
–
–
0
–
–200
CLZ
Max
to eliminate bus contention between SRAMs when sharing the same
2.8
2.8
2.8
2.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
6.0
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
0
–
–
0
–
–166
DD
Max
minimum initially before a Read or Write operation
3.5
3.5
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min Max Min Max
7.5
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
0
–
–
0
–
–133
4.0
4.0
4.0
4.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3.5
3.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
10
1
–
0
–
–
0
–
–100
CY7C1350G
4.5
4.5
4.5
4.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 10 of 18
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback