CY7C1350G-133AXC Cypress Semiconductor Corp, CY7C1350G-133AXC Datasheet - Page 5

• Manufacturer Part Number: CY7C1350G-133AXC
• Description: IC SRAM 4.5MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1350G-133AXC

• Memory Size: 4.5M (128K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 4 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 225 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 128K X 36
• Clock Frequency: 133MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Density: 4Mb
• Access Time (max): 4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 225mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2116; CY7C1350G-133AXC

Pin Definitions
Functional Overview
The CY7C1350G is a synchronous-pipelined burst SRAM
designed specifically to eliminate wait states during write/read
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the clock enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. All data outputs pass through output registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t
Accesses can be initiated by asserting all three chip enables
(CE
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
Document Number: 38-05524 Rev. *I
ZZ
DQs
DQP
MODE
V
V
V
NC
DD
DDQ
SS
Name
1
, CE
[A:D]
3
are all asserted active, (3) the write enable input signal
2
, CE
CO
I/O power supply Power supply for the I/O circuitry.
asynchronous
Power supply
synchronous
synchronous
) is 2.6 ns (250-MHz device).
3
strap pin
) active at the rising edge of the clock. If clock
Ground
Input-
Input
I/O-
I/O-
I/O
(continued)
[A:D]
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin
has an internal pull-down.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the address during the clock rise of the read cycle. The direction of the pins is controlled by OE
and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When
HIGH, DQ
during the data portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ
sequences, DQP
Mode input. Selects the burst order of the device. When tied to GND selects linear burst
sequence. When tied to V
Power supply inputs to the core of the device.
Ground for the device.
No Connects. Not internally connected to the die. 9M, 18M, 36M, 72M, 144M and 288M are
address expansion pins in this device and will be used as address pins in their respective densities.
can be used to conduct byte write
1
s
, CE
and DQP
2
[A:D]
, CE
X
is controlled by BW
3
are placed in a tri-state condition. The outputs are automatically tri-stated
) and an
DD
1
, CE
or left floating selects interleaved burst sequence.
2
,
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus, provided OE is active LOW. After
the first clock of the read access the output buffers are controlled
by OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (read/write/deselect) can
be initiated. Deselecting the device is also pipelined. Therefore,
when the SRAM is deselected at clock rise by one of the chip
enable signals, its output will tri-state following the next clock
rise.
Burst Read Accesses
The CY7C1350G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
reads without reasserting the address inputs. ADV/LD must be
driven LOW in order to load a new address into the SRAM, as
described in the
sequence of the burst counter is determined by the MODE input
signal. A LOW input on MODE selects a linear burst mode, a
HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and will wrap
around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal burst counter regardless of the state
of chip enables inputs or WE. WE is latched at the beginning of
a burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
asserted LOW. The address presented to the address inputs is
loaded into the address register. The write signals are latched
into the control logic block.
[A:D]
Description
3
correspondingly.
are all asserted active, and (3) the write signal WE is
Single Read Accesses
CY7C1350G
section above. The
s
. During write
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1
, CE
2
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