CY7C1350G-133AXC Cypress Semiconductor Corp, CY7C1350G-133AXC Datasheet - Page 4

• Manufacturer Part Number: CY7C1350G-133AXC
• Description: IC SRAM 4.5MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1350G-133AXC

• Memory Size: 4.5M (128K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 4 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 225 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 128K X 36
• Clock Frequency: 133MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Density: 4Mb
• Access Time (max): 4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 225mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2116; CY7C1350G-133AXC

Pin Configurations
Pin Definitions
Document Number: 38-05524 Rev. *I
A0, A1, A
BW
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
Name
1
2
3
[A:D]
asynchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
Input-clock
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
I/O
A
B
C
D
G
H
K
M
N
R
U
E
F
L
P
T
J
(continued)
Address inputs used to select one of the 128 K address locations. Sampled at the rising edge
of the CLK. A
Byte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/load input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD should be
driven LOW in order to load a new address.
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Output enable, asynchronous input, active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.
Clock enable input, active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
NC/576M
NC/144M
NC/1G
V
V
V
V
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
2
1
1
NC
DDQ
DDQ
DDQ
DDQ
DDQ
1
and CE
and CE
and CE
C
C
C
C
D
D
D
D
NC/72M
2
DQP
DQP
3
3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CE
V
NC
[1:0]
to select/deselect the device.
to select/deselect the device.
to select/deselect the device.
A
2
A
A
DD
2
C
C
C
C
D
D
D
D
C
D
are fed to the two-bit burst counter.
119-ball BGA Pinout
MODE
BW
BW
V
V
V
V
V
V
V
V
V
NC
A
A
A
A
3
SS
SS
SS
SS
SS
SS
SS
SS
SS
C
D
NC/18M
ADV/LD
NC/9M
CEN
CLK
V
CE
V
V
WE
NC
OE
NC
NC
A1
A0
A
4
DD
DD
DD
1
Description
BW
BW
V
V
V
V
V
V
V
V
V
NC
NC
5
A
A
A
A
SS
SS
SS
SS
SS
SS
SS
SS
SS
A
B
NC/36M
DQP
DQP
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CE
V
NC
6
A
A
A
DD
3
B
B
B
B
A
A
A
A
A
B
NC/288M
V
V
V
V
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
NC
ZZ
DDQ
DDQ
DDQ
DDQ
DDQ
7
B
B
B
B
A
A
A
A
CY7C1350G
Page 4 of 18
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