ST72T213G1B6 STMicroelectronics, ST72T213G1B6 Datasheet
ST72T213G1B6
Specifications of ST72T213G1B6
Related parts for ST72T213G1B6
ST72T213G1B6 Summary of contents
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BYTES RAM, ADC, WDG, SPI AND TIMERS User Program Memory (ROM/OTP/EPROM bytes Data RAM: 256 bytes, including 64 bytes of stack Master Reset and Power-On Reset Run, Wait, Slow, Halt and RAM Retention ...
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GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72101/ST72212/ST72213 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST72101, ST72213 and ST72212 HCMOS Microcontroller Units are members of the ST7 family. These devices are based on an industry- standard 8-bit core and feature an enhanced instruction set. They normally operate at ...
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PIN DESCRIPTION Figure 2. ST72212 Pinout (SO28 RESET 2 27 OSCIN 3 OSCOUT 26 SS/PB7 4 25 SCK/PB6 5 24 MISO/PB5 6 23 MOSI/PB4 7 22 OCMP2_A/PB3 8 21 ICAP2_A/PB2 20 9 OCMP1_A/PB1 10 19 ICAP1_A/PB0 18 ...
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ST72101/ST72212/ST72213 Table 1. ST72212 Pin Configuration Pin n° Pin n ° Pin Name SDIP32 SO28 1 1 RESET 2 2 OSCIN 3 3 OSCOUT 4 4 PB7/ PB6/SCK 6 6 PB5/MISO 7 7 PB4/MOSI ...
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Table 2. ST72213 Pin Configuration Pin n° Pin n° Pin Name SDIP32 SO28 1 1 RESET 2 2 OSCIN 3 3 OSCOUT 4 4 PB7/ PB6/SCK 6 6 PB5/MISO 7 7 PB4/MOSI ...
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ST72101/ST72212/ST72213 Table 3. ST72101 Pin Configuration Pin n° Pin n° Pin Name SDIP32 SO28 1 1 RESET 2 2 OSCIN 3 3 OSCOUT 4 4 PB7/ PB6/SCK 6 6 PB5/MISO 7 7 PB4/MOSI ...
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EXTERNAL CONNECTIONS The following figure shows the recommended ex- ternal connections for the device. The V pin is only used for programming OTP PP and EPROM devices and must be tied to ground in user mode. The 10 nF ...
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ST72101/ST72212/ST72213 1.4 MEMORY MAP Figure 9. Memory Map 0000h HW Registers (see 007Fh 0080h 256 Bytes RAM 017Fh 0180h DFFFh E000h Program Memory F000h 4K Bytes Program Memory FFDFh FFE0h Interrupt & Reset Vectors (see FFFFh Table 4. Interrupt Vector ...
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Table 5. Hardware Register Memory Map Block Register Address Name 0000h PCDR 0001h Port C PCDDR 0002h PCOR 0003h 0004h PBDR 0005h Port B PBDDR 0006h PBOR 0007h 0008h PADR 0009h Port A PADDR 000Ah PAOR 000Bh to 001Fh 0020h ...
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ST72101/ST72212/ST72213 Block Register Address Name 0041h TBCR2 0042h TBCR1 0043h TBSR 0044h-0045h TBIC1HR TBIC1LR 0046h-0047h TBOC1HR TBOC1LR 1) 0048h-0049h Timer B TBCHR TBCLR 004Ah-004Bh TBACHR TBACLR 004Ch-004Dh TBIC2HR TBIC2LR 004Eh-004Fh TBOC2HR TBOC2LR 0050h to 006Fh 0070h ADCDR 2) ADC 0071h ...
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CENTRAL PROCESSING UNIT 2.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 MAIN FEATURES 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit ...
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ST72101/ST72212/ST72213 CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. ...
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CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free ...
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ST72101/ST72212/ST72213 3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES 3.1 CLOCK SYSTEM 3.1.1 General Description The MCU accepts either a Crystal or Ceramic res- onator external clock signal to drive the in- ternal oscillator. The internal clock (f ...
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RESET 3.2.1 Introduction There are three sources of Reset: – RESET pin (external source) – Power-On Reset (Internal source) – WATCHDOG (Internal Source) The Reset Service Routine vector is located at ad- dress FFFEh-FFFFh. 3.2.2 External Reset The RESET ...
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ST72101/ST72212/ST72213 4 INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in ...
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INTERRUPTS (Cont’d) Figure 16. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION N I BIT SET? Y FETCH NEXT INSTRUCTION N IRET? Y LOAD PC FROM INTERRUPT VECTOR RESTORE PC FROM STACK THIS CLEARS I BIT BY DEFAULT ...
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ST72101/ST72212/ST72213 Table 7. Interrupt Mapping Source Description Block RESET Reset TRAP Software EI0 External Interrupt PA0:PA7 EI1 External Interrupt PB0:PB7, PC0:PC5 Transfer Complete SPI Mode Fault Input Capture 1 Output Compare 1 TIMER A Input Capture 2 Output Compare 2 ...
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POWER SAVING MODES 4.4.1 Introduction There are three Power Saving modes. Slow Mode is selected by setting the relevant bits in the Mis- cellaneous register. Wait and Halt modes may be entered using the WFI and HALT instructions. 4.4.2 ...
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ST72101/ST72212/ST72213 POWER SAVING MODES (Cont’d) 4.4.4 Halt Mode The Halt mode is the MCU lowest power con- sumption mode. The Halt mode is entered by exe- cuting the HALT instruction. The internal oscillator is then turned off, causing all internal ...
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MISCELLANEOUS REGISTER The Miscellaneous register allows to select the SLOW operating mode, the polarity of external in- terrupt requests and to output the internal clock. Register Address: 0020h — Read /Write Reset Value: 0000 0000 (00h) 7 PEI3 PEI2 ...
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ST72101/ST72212/ST72213 5 ON-CHIP PERIPHERALS 5.1 I/O PORTS 5.1.1 Introduction The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – analog signal input (ADC) – alternate signal input/output for the ...
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I/O PORTS (Cont’d) 5.1.2.4 Analog Alternate Function When the pin is used as an ADC input the I/O must be configured as input, floating. The analog multi- plexer (controlled by the ADC registers) switches the analog voltage present on the ...
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ST72101/ST72212/ST72213 I/O PORTS (Cont’d) . Figure 20 I/O Block Diagram ALTERNATE OUTPUT DR LATCH DDR LATCH OR LATCH ( ABLE BELOW OR SEL DDR SEL DR SEL ALTERNATE INPUT POLARITY SEL EXTERNAL INTERRUPT SOURCE (EIx) Table 10. Port ...
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Table 11. Port Configuration Port Pin Name Port A PA0:PA7 Floating* Port B PB0:PB7 Floating* Port C PC0:PC5 Floating* *Reset State Input (DDR = Floating with Interrupt Pull-up with Interrupt Open Drain (Logic ...
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ST72101/ST72212/ST72213 I/O PORTS (Cont’d) 5.1.4 Register Description 5.1.4.1 Data registers Port A Data Register (PADR) Port B Data Register (PBDR) Port C Data Register (PCDR) Read /Write Reset Value: 0000 0000 (00h Bit 7:0 ...
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I/O PORTS (Cont’d) Table 12. I/O Port Register Map and Reset Values Address Register 7 Label (Hex.) PCDR D7 0000h 0 Reset Value PCDDR DD7 0001h 0 Reset Value PCOR O7 0002h 0 Reset Value PBDR D7 0004h 0 Reset ...
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ST72101/ST72212/ST72213 5.2 WATCHDOG TIMER (WDG) 5.2.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon ...
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WATCHDOG TIMER (Cont’d) 5.2.3 Functional Description The counter value stored in the CR register (bits T6:T0), is decremented every 12,288 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. If ...
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ST72101/ST72212/ST72213 5.3 16-BIT TIMER 5.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths two input sig- nals ...
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TIMER (Cont’d) Figure 22. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 OCF2 ICIE OCIE TOIE FOLV2 FOLV1 (Control Register 1) ...
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ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read Byte value at ...
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TIMER (Cont’d) Figure 23. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 24. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER ...
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ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d) 5.3.3.3 Input Capture In this section, the index may because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are ...
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TIMER (Cont’d) Figure 26. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 27. Input Capture Timing Diagram TIMER CLOCK FF01 COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER ...
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ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d) 5.3.3.4 Output Compare In this section, the index may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform ...
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TIMER (Cont’d) Notes: 1. After a processor write cycle to the reg- ister, the output compare function is inhibited until the register is also written the bit is ...
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ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d) Figure 29. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCR i ) OUTPUT COMPARE FLAG i (OCF i ) OCMP i PIN (OLVL i =1) Figure 30. Output Compare ...
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TIMER (Cont’d) 5.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input ...
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ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d) Figure 31. One Pulse Mode Timing Example FFFC FFFD FFFE COUNTER ICAP1 OCMP1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 32. Pulse Width Modulation Mode Timing Example FFFC FFFD FFFE COUNTER 34E2 OCMP1 compare2 Note: OC1R=2ED0h, OC2R=34E2, ...
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TIMER (Cont’d) 5.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode ...
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ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d) 5.3.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode ...
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TIMER (Cont’d) 5.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ...
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ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the ...
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TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ICF1 Input Capture Flag input capture (reset ...
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ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 2 ...
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TIMER (Cont’d) Table 16. 16-Bit Timer Register Map and Reset Values Address Register 7 Name (Hex.) TimerA: 32 CR1 ICIE TimerB: 42 Reset Value 0 TimerA: 31 CR2 OC1E TimerB: 41 Reset Value 0 TimerA ICF1 TimerB: ...
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ST72101/ST72212/ST72213 5.4 SERIAL PERIPHERAL INTERFACE (SPI) 5.4.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 34. Serial Peripheral Interface Block Diagram Read Read Buffer MOSI MISO 8-Bit Shift Register Write SCK SS Internal Bus DR SPIF WCOL SPIE SPE MASTER CONTROL SERIAL CLOCK GENERATOR ST72101/ST72212/ST72213 IT request SR MODF - ...
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ST72101/ST72212/ST72213 SERIAL PERIPHERAL INTERFACE (Cont’d) 5.4.4 Functional Description Figure 1 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register (DR) Refer ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 5.4.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure – ...
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ST72101/ST72212/ST72213 SERIAL PERIPHERAL INTERFACE (Cont’d) 5.4.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to syn- chronize the data transfer during a sequence of ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 36. Data Clock Timing Diagram SCLK (with CPOL = 1) SCLK (with CPOL = 0) MSBit MISO (from master) MSBit MOSI (from slave) SS (to slave) CAPTURE STROBE CPOL = 1 CPOL = 0 MSBit ...
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ST72101/ST72212/ST72213 SERIAL PERIPHERAL INTERFACE (Cont’d) 5.4.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak- ing place with an external device. When this hap- pens, the ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 5.4.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – ...
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ST72101/ST72212/ST72213 SERIAL PERIPHERAL INTERFACE (Cont’d) 5.4.4.7 Single Master and Multimaster Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured, using an MCU as ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 5.4.5 Low Power Modes Mode No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. HALT In HALT mode, the SPI is inactive. SPI operation resumes ...
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ST72101/ST72212/ST72213 SERIAL PERIPHERAL INTERFACE (Cont’d) 5.4.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) 7 SPIF WCOL - MODF - Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been ...
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ST72101/ST72212/ST72213 SERIAL PERIPHERAL INTERFACE (Cont’d) Table 18. SPI Register Map and Reset Values Address Register 7 Name (Hex Reset Value x CR SPIE 22 Reset Value 0 SR SPIF 23 Reset Value 0 62/ ...
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A/D CONVERTER (ADC) 5.5.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer ...
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ST72101/ST72212/ST72213 8-BIT A/D CONVERTER (ADC) (Cont’d) 5.5.3 Functional Description The high level reference voltage V connected externally to the V DD reference voltage V must be connected exter- SSA nally to the V pin. In some devices (refer to de- ...
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A/D CONVERTER (ADC) (Cont’d) 5.5.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) 7 COCO - ADON 0 - Bit 7 = COCO Conversion Complete This bit is set by hardware cleared by soft- ...
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ST72101/ST72212/ST72213 6 INSTRUCTION SET 6.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld ...
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ST7 ADDRESSING MODES (Cont’d) 6.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For ...
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ST72101/ST72212/ST72213 ST7 ADDRESSING MODES (Cont’d) 6.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index ...
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INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and ...
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ST72101/ST72212/ST72213 INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) ...
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INSTRUCTION GROUPS (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2’s compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset carry ...
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ST72101/ST72212/ST72213 7 ELECTRICAL CHARACTERISTICS 7.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than ...
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RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A V Operating Supply Voltage DD f Oscillator Frequency OSC Note 1: A/D operation and Oscillator start-up are not guaranteed below 1MHz. Figure 41. Maximum Operating Frequency (f FUNCTIONALITY NOT GUARANTEED ...
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ST72101/ST72212/ST72213 7.3 DC ELECTRICAL CHARACTERISTICS (T = -40°C to +125°C and Symbol Parameter Input Low Level Voltage V IL All Input pins Input High Level Voltage V IH All Input pins 1) Hysteresis Voltage V HYS All ...
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RESET CHARACTERISTICS o (T =-40...+125 C and V =5V±10% unless otherwise specified Symbol Parameter R Reset Weak Pull- Pulse duration generated by watch- t RESET dog and POR reset Minimum pulse duration to be ap- ...
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ST72101/ST72212/ST72213 7.6 A/D CONVERTER CHARACTERISTICS (ST72212 and ST72213 only -40°C to +125°C and Symbol Parameter T Sample Duration SAMPLE Res ADC Resolution DLE Differential Linearity Error* ILE Integral Linearity Error* V Analog Input Voltage AIN ...
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A/D CONVERTER CHARACTERISTICS (Cont’d) Figure 42. ADC conversion characteristics 255 254 253 252 251 250 code out LSB (ideal Offset Error OSE Offset Error OSE ( ...
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ST72101/ST72212/ST72213 7.7 SPI CHARACTERISTICS Ref. Symbol Parameter f SPI frequency SPI 1 t SPI clock period SPI 2 t Enable lead time Lead 3 t Enable lag time Lag 4 t Clock (SCK) high time SPI_H 5 t Clock (SCK) ...
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SPI CHARACTERISTICS (Cont’d) Measurement points are Figure 44. SPI Master Timing Diagram CPHA=0, CPOL=1 SS (INPUT) SCK (OUTPUT) MISO (INPUT) 6 MOSI (OUTPUT) 10 Figure 45. SPI Master Timing Diagram CPHA=1, CPOL=0 SS (INPUT) SCK (OUTPUT) ...
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ST72101/ST72212/ST72213 SPI CHARACTERISTICS (Cont’d) Measurement points are Figure 47. SPI Slave Timing Diagram CPHA=0, CPOL=0 SS (INPUT) 2 SCK (INPUT) 4 MISO HIGH-Z D7-OUT (OUTPUT) 8 MOSI D7-IN (INPUT) 6 Figure 48. SPI Slave Timing Diagram ...
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GENERAL INFORMATION 8.1 EPROM ERASURE EPROM version devices are erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current recommended ...
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ST72101/ST72212/ST72213 Figure 52. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width Figure 53. 32-Pin Shrink Ceramic Dual In-Line Package 82/ CDIP32SW mm inches Dim. Min Typ Max ...
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... All un- used bytes must be set to FFh. The selected options are communicated to STMi- croelectronics using the correctly completed OP- TION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points. / XXX Code name (defined by STMicroelectronics standard 0 to +70° ...
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... Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phone Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STMicroelectronics references Device: Package: Temperature Range: Special Marking: Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character count: SDIP32: ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...