ST72T213G1B6 STMicroelectronics, ST72T213G1B6 Datasheet - Page 31

• Manufacturer Part Number: ST72T213G1B6
• Description: 8-bit Microcontrollers - MCU OTP EPROM 4K SPI
• Manufacturer: STMicroelectronics

Specifications of ST72T213G1B6

• Rohs: yes
• Core: ST7
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 5.5 V
• Package / Case: PDIP-32
• Mounting Style: Through Hole
• A/d Bit Size: 8 bit
• A/d Channels Available: 6
• Interface Type: SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 22
• Number Of Timers: 1
• On-chip Dac: No
• Program Memory Type: OTP EPROM
• Factory Pack Quantity: 16
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.5 V

WATCHDOG TIMER (Cont’d)
5.2.3 Functional Description
The counter value stored in the CR register (bits
T6:T0), is decremented every 12,288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T6:T0) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
– The T5:T0 bits contain the number of increments
Table 13. Watchdog Timing (f
Notes: Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
Table 14. Watchdog Timer Register Map and Reset Values
diate reset
which represents the time delay before the
watchdog produces a reset.
Max
Min
Address
(Hex.)
0024h
Table
1):
CR Register
initial value
Reset Value
Register
WDGCR
FFh
C0h
Label
WDGA
7
WDG timeout period
0
CPU
= 8 MHz)
98.304
1.536
(ms)
T6
6
1
T5
5
1
5.2.4 Low Power Modes
5.2.5 Interrupts
None.
5.2.6 Register Description
CONTROL REGISTER (CR)
Read /Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = WDGA Activation bit .
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
Mode
WAIT
HALT
WDGA
7
T4
4
1
T6
Description
No effect on Watchdog.
Immediate reset generation as soon as
the HALT instruction is executed if the
Watchdog is activated (WDGA bit is
set).
T3
3
1
T5
ST72101/ST72212/ST72213
T4
T2
2
1
T3
T2
T1
1
1
T1
31
T0
0
1
31/85
T0
0