MT46V8M16TG-6T L:D TR Micron Technology Inc, MT46V8M16TG-6T L:D TR Datasheet - Page 22

• Manufacturer Part Number: MT46V8M16TG-6T L:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V8M16TG-6T L:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1042-2

Table 19:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
AC Characteristics
Parameter
Access window of DQ from CK/CK#
CK high-level width
Clock cycle time
CK low-level width
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS–DQ skew, DQS to last DQ valid, per group, per
access
WRITE command to first DQS latching transition
DQ and DM input setup time relative to DQS
DQS falling edge from CK rising - hold time
DQS falling edge to CK rising - setup time
Half-clock period
Data-out High-Z window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input pulse width (for each
input)
Address and control input setup time (fast slew rate)
Address and control input setup time (slow slew rate)
Data-out Low-Z window from CK/CK#
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
Data hold skew factor
ACTIVE-to-READ with auto precharge command
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE/AUTO REFRESH command period
ACTIVE-to-READ or WRITE delay
REFRESH-to-REFRESH
command interval
Average periodic refresh
interval
AUTO REFRESH command
period
PRECHARGE command period
DQS read preamble
Electrical Characteristics and Recommended AC Operating Conditions (-6, -6T, -75E)
Notes: 1–6, 15–18, 34 apply to entire table; Notes appear on pages 26–32;
0°C ≤ T
A
≤ +70°C; V
CL = 2.5
CL = 2
128Mb
256Mb, 512Mb, 1Gb
128Mb
256Mb, 512Mb, 1Gb
128Mb, 256Mb, 512Mb
1Gb
DD
Q = +2.5V ±0.2V, V
DD
Symbol
t
t
CK (2.5)
t
t
DQSCK
t
t
t
t
t
t
t
t
CK (2)
DQSH
DQSQ
t
= +2.5V ±0.2V
DIPW
DQSL
DQSS
t
t
t
t
t
t
t
t
t
t
RPRE
MRD
REFC
REFC
t
t
t
t
DSH
t
t
QHS
RCD
REFI
REFI
t
t
t
IPW
t
t
RAP
RAS
t
t
DSS
t
RFC
RFC
t
DH
QH
AC
CH
IH
IH
DS
HP
HZ
IS
IS
RC
RP
CL
LZ
F
S
22
F
S
–0.70 +0.70 –0.70 +0.70 –0.75 +0.75
t
t
Min
1.75
0.75
0.75
-6 (FBGA)
0.45
0.45
0.45
–0.6
0.35
0.35
0.75
0.45
t
–0.7
HP -
QHS
7.5
0.2
0.2
t
0.8
2.2
0.8
0.9
CH,
12
15
42
60
15
72
15
CL
6
–
–
–
–
–
–
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Electrical Specifications – DC and AC
70,00
140.6
Max
0.55
0.55
+0.6
1.25
+0.7
0.50
70.3
15.6
0.4
7.8
1.1
13
13
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
128Mb: x4, x8, x16 DDR SDRAM
t
t
Min
0.45
0.45
0.45
1.75
–0.6
0.35
0.35
0.75
0.45
t
0.75
0.75
–0.7
-6T (TSOP)
QHS
120
HP -
7.5
0.2
0.2
t
0.8
2.2
0.8
0.9
CH,
12
15
42
60
15
72
15
CL
6
–
–
–
–
–
–
–
70,00
140.6
Max
+0.6
0.55
0.55
0.45
1.25
+0.7
0.55
70.3
15.6
7.8
1.1
13
13
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
–
–
–
–
–
–0.75 +0.75
–0.75
t
t
Min
©2004 Micron Technology, Inc. All rights reserved.
0.45
0.45
1.75
0.35
0.35
0.75
t
0.90
0.90
QHS
HP -
7.5
7.5
0.5
0.5
0.2
0.2
t
2.2
0.9
CH,
15
15
40
60
15
75
15
CL
1
1
–
–
–
–
–
–
–
–
-75E
+0.75
120,0
140.6
Max
0.55
0.55
1.25
0.75
70.3
15.6
0.5
7.8
1.1
13
13
00
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Units Notes
t
t
t
t
t
t
t
t
ns
CK
ns
ns
CK
ns
ns
ns
CK
CK
ns
CK
ns
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
ns
ns
ns
CK
46, 52
19, 43
46, 52
27, 32
26, 27
27, 32
19, 43
26, 27
36, 54
32
35
15
15
24
24
24
24
50
50
31
31
44