MT46V8M16TG-6T L:D TR Micron Technology Inc, MT46V8M16TG-6T L:D TR Datasheet - Page 47

• Manufacturer Part Number: MT46V8M16TG-6T L:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V8M16TG-6T L:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1042-2

CAS Latency (CL)
Figure 22:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
CAS Latency
Note:
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first bit of output data. The latency can be set to 2, 2.5, or 3 (-5B
only) clocks, as shown in Figure 22. Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Table 32 on page 48 indi-
cates the operating frequencies at which each CL setting can be used.
COMMAND
COMMAND
COMMAND
BL = 4 in the cases shown; shown with nominal
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
READ
READ
READ
T0
T0
T0
CL = 2
CL = 2.5
CL = 3
47
NOP
NOP
NOP
T1
T1
T1
TRANSITIONING DATA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
T2
NOP
NOP
NOP
T2
128Mb: x4, x8, x16 DDR SDRAM
t
AC,
T2n
T2n
t
DQSCK, and
T3
T3
NOP
NOP
NOP
T3
DON’T CARE
©2004 Micron Technology, Inc. All rights reserved.
T3n
T3n
T3n
t
DQSQ.
Operations