MT46V8M16TG-6T L:D TR Micron Technology Inc, MT46V8M16TG-6T L:D TR Datasheet - Page 69

• Manufacturer Part Number: MT46V8M16TG-6T L:D TR
• Description: IC DDR SDRAM 128MBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT46V8M16TG-6T L:D TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1042-2

Figure 42:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
COMMAND
ADDRESS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE-to-READ – Odd Number of Data, Interrupting
Notes:
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
1. DI b = data-in for column b; DO n = data-out for column n.
2. An interrupted burst of 4 is shown; one data element is written.
3.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
6. If the burst of 8 is used, DM and DQS are required at T3–T3n because the READ command
t
the last two data elements).
will not mask these data elements.
WTR is referenced from the first positive CK edge after the last desired data-in pair (not
DI
b
NOP
T1
DI
b
DI
b
T1n
NOP
T2
t
WTR
T2n
69
Bank a,
READ
Col n
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3n
128Mb: x4, x8, x16 DDR SDRAM
CL = 2
CL = 2
CL = 2
T4
NOP
DON’T CARE
T5
©2004 Micron Technology, Inc. All rights reserved.
NOP
DO
DO
DO
n
n
n
TRANSITIONING DATA
T5n
Operations
T6
NOP
T6n